20123a8838
Switch to use common version of PCR asl. BUG=NONE TEST=Boot up into chrome OS properly on cannonlake rvp platform. Change-Id: I4975704434d4743bcc0fb6062115da349166c3a6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
51 lines
1.1 KiB
Plaintext
51 lines
1.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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/* eMMC, SD Card */
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#include "scs.asl"
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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/* GPIO controller */
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#include "gpio.asl"
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/* LPC 0:1f.0 */
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#include "lpc.asl"
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/* PCH HDA */
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#include "pch_hda.asl"
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/* Serial IO */
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#include "serialio.asl"
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/* SMBus 0:1f.3 */
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#include "smbus.asl"
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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/* CNVi */
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#include "cnvi.asl"
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