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20ffc03efaea79a74bdb82adb5be67a58afe2e64
system76-coreboot/src/southbridge
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Marc Jones 2c39c4c5a9 There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12 00:03:26 +00:00
..
amd
There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
2008-07-12 00:03:26 +00:00
broadcom
Rename almost all occurences of LinuxBIOS to coreboot.
2008-01-18 15:08:58 +00:00
intel
Implement GPIO configuration routines for the Intel 3100 southbridge,
2008-05-07 21:57:12 +00:00
nvidia
This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
2008-04-23 00:40:39 +00:00
ricoh/rl5c476
Rename almost all occurences of LinuxBIOS to coreboot.
2008-01-18 15:08:58 +00:00
sis/sis966
Please bear with me - another rename checkin. This qualifies as trivial, no
2008-01-18 10:35:56 +00:00
via
Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.
2008-06-20 00:01:14 +00:00
winbond/w83c553
Updating FSF address in the code.
2005-10-05 18:17:45 +00:00
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