21cde8b832
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
98 lines
3.5 KiB
C
98 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <northbridge/amd/pi/agesawrapper.h>
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#include <amdlib.h>
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800
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* legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
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* ACPI) are set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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/* last address before processor local APIC at FEE00000 */
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PciData = 0x00FEDF00;
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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/* lowest NP address is HPET at FED00000 */
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PciData = (0xFED00000 >> 8) | 3;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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void amd_initmmio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO
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configuration base Address MSR register.
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*/
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MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \
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(LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
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LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
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/* For serial port */
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PciData = 0xFF03FFD5;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44);
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Set ROM cache onto WP to decrease post time */
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MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
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LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
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0x800ull;
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LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
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if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
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LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
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MsrReg |= 1 << 11;
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LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
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}
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}
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