0d8d482f63
This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1] Some AMD south bridge can write bigger data when saving S3 info. In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size. AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig' and then can be overridden in the Kconfig for specific southbridges that support larger size. I have tested on AMD Parmer and Thatcher. We will release a new board whose south bridge can transfer more than 4 bytes each time. [1] http://review.coreboot.org/#/c/2306/ Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3413 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
24 lines
791 B
Plaintext
24 lines
791 B
Plaintext
source src/southbridge/amd/amd8111/Kconfig
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source src/southbridge/amd/amd8131/Kconfig
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source src/southbridge/amd/cs5536/Kconfig
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#source src/southbridge/amd/amd8131-disable/Kconfig
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source src/southbridge/amd/amd8132/Kconfig
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source src/southbridge/amd/amd8151/Kconfig
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source src/southbridge/amd/cs5530/Kconfig
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source src/southbridge/amd/cs5535/Kconfig
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source src/southbridge/amd/rs690/Kconfig
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source src/southbridge/amd/sb600/Kconfig
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source src/southbridge/amd/rs780/Kconfig
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source src/southbridge/amd/sb700/Kconfig
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source src/southbridge/amd/sb800/Kconfig
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source src/southbridge/amd/cimx/Kconfig
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source src/southbridge/amd/agesa/Kconfig
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source src/southbridge/amd/sr5650/Kconfig
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config SPI_FLASH
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bool
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default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA
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config AMD_SB_SPI_TX_LEN
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int
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default 4
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