235daa4bf6
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
126 lines
3.0 KiB
C
126 lines
3.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Uart setup helpers for Allwinner SoCs
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*
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*
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*/
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#include "uart.h"
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#include <arch/io.h>
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#include <console/uart.h>
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#include <drivers/uart/uart8250reg.h>
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/**
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* \brief Configure line control settings for UART
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*/
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static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits,
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enum uart_parity parity, u8 stop_bits)
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{
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u32 reg32;
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u16 div;
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div = (u16) uart_baudrate_divisor(baud_rate,
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uart_platform_refclk(), 16);
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/* Enable access to Divisor Latch register */
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write32(&uart->lcr, UART8250_LCR_DLAB);
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/* Set baudrate */
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write32(&uart->dlh, (div >> 8) & 0xff);
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write32(&uart->dll, div & 0xff);
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/* Set line control */
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reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
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switch (parity) {
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case UART_PARITY_ODD:
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reg32 |= UART8250_LCR_PEN;
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break;
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case UART_PARITY_EVEN:
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reg32 |= UART8250_LCR_PEN;
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reg32 |= UART8250_LCR_EPS;
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break;
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case UART_PARITY_NONE: /* Fall through */
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default:
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break;
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}
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write32(&uart->lcr, reg32);
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}
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static void a10_uart_enable_fifos(struct a10_uart *uart)
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{
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write32(&uart->fcr, UART8250_FCR_FIFO_EN);
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}
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static int tx_fifo_full(struct a10_uart *uart)
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{
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/* This may be a misnomer, or a typo in the datasheet. THRE indicates
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* that the TX register is empty, not that the FIFO is not full, but
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* this may be due to a datasheet typo. Keep the current name to signal
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* intent. */
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return !(read32(&uart->lsr) & UART8250_LSR_THRE);
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}
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static int rx_fifo_empty(struct a10_uart *uart)
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{
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return !(read32(&uart->lsr) & UART8250_LSR_DR);
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}
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/**
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* \brief Read a single byte from the UART.
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*
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* Blocks until at least a byte is available.
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*/
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static u8 a10_uart_rx_blocking(struct a10_uart *uart)
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{
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while (rx_fifo_empty(uart));
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return read32(&uart->rbr);
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}
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/**
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* \brief Write a single byte to the UART.
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*
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* Blocks until there is space in the FIFO.
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*/
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static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
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{
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while (tx_fifo_full(uart));
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return write32(&uart->thr, data);
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}
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void uart_init(int idx)
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{
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struct a10_uart *uart_base = uart_platform_baseptr(idx);
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/* Use default 8N1 encoding */
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a10_uart_configure(uart_base, get_uart_baudrate(),
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8, UART_PARITY_NONE, 1);
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a10_uart_enable_fifos(uart_base);
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}
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unsigned char uart_rx_byte(int idx)
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{
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return a10_uart_rx_blocking(uart_platform_baseptr(idx));
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}
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void uart_tx_byte(int idx, unsigned char data)
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{
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a10_uart_tx_blocking(uart_platform_baseptr(idx), data);
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}
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void uart_tx_flush(int idx)
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{
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}
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