Aaron Durbin 23f50166c6 haswell: enable ROM caching ...

If ROM caching is selected the haswell CPU initialization code
will enable ROM caching after all other CPU threads are brought
up.

Change-Id: I75424bb75174bfeca001468c3272e6375e925122
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2013-04-03 19:26:05 +02:00

..

arch

Add PXE ROM selection to Kconfig menu

2013-04-03 18:01:44 +02:00

console

console: Make use of CONFIG_USE_OPTION_TABLE

2013-04-01 20:54:48 +02:00

cpu

haswell: enable ROM caching

2013-04-03 19:26:05 +02:00

device

Add PXE ROM selection to Kconfig menu

2013-04-03 18:01:44 +02:00

drivers

x86: Unify arch/io.h and arch/romcc_io.h

2013-03-22 00:00:09 +01:00

ec

x86: Unify arch/io.h and arch/romcc_io.h

2013-03-22 00:00:09 +01:00

include

intel/microcode.h: Fix typo in comment: micr*o*code

2013-04-03 19:19:09 +02:00

lib

lynxpoint: Move ACPI NVS into separate CBMEM table

2013-04-01 23:35:48 +02:00

mainboard

ASRock E350M1: Kconfig: Remove WARNINGS_ARE_ERRORS to treat warnings as errors

2013-04-03 17:20:03 +02:00

northbridge

sandybridge: add option to mark graphics memory write-combining.

2013-03-29 20:00:39 +01:00

southbridge

lynxpoint: Move ACPI NVS into separate CBMEM table

2013-04-01 23:35:48 +02:00

superio

Winbond W83627HF: Rename and move ASL snippet to acpi/superio.asl

2013-04-01 21:09:24 +02:00

vendorcode

chromeos: honor MOCK_TPM=1

2013-04-01 23:26:17 +02:00

Kconfig

dynamic cbmem: fix memconsole and timestamps

2013-03-23 19:44:25 +01:00