244848462d
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
137 lines
3.0 KiB
C
137 lines
3.0 KiB
C
/*
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* SMI handler for Hudson southbridges
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*
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* Subject to the GNU GPL v2, or (at your option) any later version.
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*/
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <delay.h>
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#include <soc/hudson.h>
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#include <soc/smi.h>
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#define SMI_0x88_ACPI_COMMAND (1 << 11)
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enum smi_source {
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SMI_SOURCE_SCI = (1 << 0),
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SMI_SOURCE_GPE = (1 << 1),
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SMI_SOURCE_0x84 = (1 << 2),
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SMI_SOURCE_0x88 = (1 << 3),
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SMI_SOURCE_IRQ_TRAP = (1 << 4),
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SMI_SOURCE_0x90 = (1 << 5)
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};
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static void hudson_apmc_smi_handler(void)
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{
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u32 reg32;
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const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);
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switch (cmd) {
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case ACPI_SMI_CMD_ENABLE:
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reg32 = inl(ACPI_PM1_CNT_BLK);
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reg32 |= (1 << 0); /* SCI_EN */
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outl(reg32, ACPI_PM1_CNT_BLK);
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break;
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case ACPI_SMI_CMD_DISABLE:
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reg32 = inl(ACPI_PM1_CNT_BLK);
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reg32 &= ~(1 << 0); /* clear SCI_EN */
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outl(ACPI_PM1_CNT_BLK, reg32);
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break;
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}
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mainboard_smi_apmc(cmd);
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}
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int southbridge_io_trap_handler(int smif)
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{
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return 0;
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}
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static void process_smi_sci(void)
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{
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const uint32_t status = smi_read32(0x10);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x10, status);
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}
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static void process_gpe_smi(void)
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{
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const uint32_t status = smi_read32(0x80);
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const uint32_t gevent_mask = (1 << 24) - 1;
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/* Only Bits [23:0] indicate GEVENT SMIs. */
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if (status & gevent_mask) {
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/* A GEVENT SMI occurred */
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mainboard_smi_gpi(status & gevent_mask);
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}
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x80, status);
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}
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static void process_smi_0x84(void)
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{
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const uint32_t status = smi_read32(0x84);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x84, status);
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}
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static void process_smi_0x88(void)
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{
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const uint32_t status = smi_read32(0x88);
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if (status & SMI_0x88_ACPI_COMMAND) {
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/* Command received via ACPI SMI command port */
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hudson_apmc_smi_handler();
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}
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x88, status);
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}
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static void process_smi_0x8c(void)
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{
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const uint32_t status = smi_read32(0x8c);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x8c, status);
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}
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static void process_smi_0x90(void)
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{
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const uint32_t status = smi_read32(0x90);
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/* Clear events to prevent re-entering SMI if event isn't handled */
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smi_write32(0x90, status);
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}
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void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
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{
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const uint16_t smi_src = smi_read16(0x94);
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if (smi_src & SMI_SOURCE_SCI)
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process_smi_sci();
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if (smi_src & SMI_SOURCE_GPE)
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process_gpe_smi();
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if (smi_src & SMI_SOURCE_0x84)
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process_smi_0x84();
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if (smi_src & SMI_SOURCE_0x88)
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process_smi_0x88();
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if (smi_src & SMI_SOURCE_IRQ_TRAP)
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process_smi_0x8c();
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if (smi_src & SMI_SOURCE_0x90)
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process_smi_0x90();
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}
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void southbridge_smi_set_eos(void)
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{
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uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
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reg |= SMITRG0_EOS;
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smi_write32(SMI_REG_SMITRIG0, reg);
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}
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