252111d433
If microcode.c is built by romcc, this indicates that we are running microcode updates in the bootblock (e.g. before enabling cache as ram). In this case we did not enable any consoles yet, so we don't output anything. This patch removes inclusion of the unnecessary console/console.h for that case, which was breaking with certain configurations. Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/988 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000 Ronald G. Minnich
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Microcode update for Intel PIII and later CPUs */
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#include <stdint.h>
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#if !defined(__ROMCC__)
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#include <console/console.h>
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#endif
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/microcode.h>
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struct microcode {
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u32 hdrver; /* Header Version */
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u32 rev; /* Update Revision */
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u32 date; /* Date */
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u32 sig; /* Processor Signature */
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u32 cksum; /* Checksum */
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u32 ldrver; /* Loader Revision */
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u32 pf; /* Processor Flags */
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u32 data_size; /* Data Size */
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u32 total_size; /* Total Size */
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u32 reserved[3];
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};
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static inline u32 read_microcode_rev(void)
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{
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/* Some Intel CPUs can be very finicky about the
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* CPUID sequence used. So this is implemented in
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* assembly so that it works reliably.
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*/
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msr_t msr;
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asm volatile (
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"xorl %%eax, %%eax\n\t"
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"xorl %%edx, %%edx\n\t"
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"movl $0x8b, %%ecx\n\t"
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"wrmsr\n\t"
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"movl $0x01, %%eax\n\t"
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"cpuid\n\t"
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"movl $0x08b, %%ecx\n\t"
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"rdmsr \n\t"
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: /* outputs */
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"=a" (msr.lo), "=d" (msr.hi)
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: /* inputs */
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: /* trashed */
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"ecx"
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);
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return msr.hi;
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}
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void intel_update_microcode(const void *microcode_updates)
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{
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u32 eax;
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u32 pf, rev, sig;
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unsigned int x86_model, x86_family;
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const struct microcode *m;
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const char *c;
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msr_t msr;
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/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
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msr.lo = 0;
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msr.hi = 0;
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wrmsr(0x8B, msr);
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eax = cpuid_eax(1);
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msr = rdmsr(0x8B);
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rev = msr.hi;
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x86_model = (eax >>4) & 0x0f;
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x86_family = (eax >>8) & 0x0f;
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sig = eax;
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pf = 0;
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if ((x86_model >= 5)||(x86_family>6)) {
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msr = rdmsr(0x17);
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pf = 1 << ((msr.hi >> 18) & 7);
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}
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#if !defined(__ROMCC__)
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/* If this code is compiled with ROMCC we're probably in
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* the bootblock and don't have console output yet.
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*/
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printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
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sig, pf, rev);
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#endif
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m = microcode_updates;
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for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
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if ((m->sig == sig) && (m->pf & pf)) {
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unsigned int new_rev;
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msr.lo = (unsigned long)c + sizeof(struct microcode);
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msr.hi = 0;
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wrmsr(0x79, msr);
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/* Read back the new microcode version */
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new_rev = read_microcode_rev();
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "microcode: updated to revision "
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"0x%x date=%04x-%02x-%02x\n", new_rev,
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m->date & 0xffff, (m->date >> 16) & 0xff,
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(m->date >> 24) & 0xff);
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#endif
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break;
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}
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if (m->total_size) {
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c += m->total_size;
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} else {
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#if !defined(__ROMCC__)
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printk(BIOS_WARNING, "Microcode has no valid size field!\n");
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#endif
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c += 2048;
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}
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}
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}
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