2560dbdd50
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
141 lines
3.0 KiB
C
141 lines
3.0 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
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#include "northbridge/intel/e7501/raminit.h"
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#include "cpu/intel/model_f2x/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/intel/e7501/debug.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void hard_reset(void)
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{
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outb(0x0e, 0x0cf9);
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}
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static void memreset_setup(void)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/e7501/raminit.c"
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#include "northbridge/intel/e7501/reset_test.c"
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#include "sdram/generic_sdram.c"
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{
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.d0 = PCI_DEV(0, 0, 0),
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.d0f1 = PCI_DEV(0, 0, 1),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
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.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
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},
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};
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if (bist == 0) {
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/* Skip this if there was a built in self test failure */
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early_mtrr_init();
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enable_lapic();
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init_timer();
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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// setup_default_resource_map();
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#if 0
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print_pci_devices();
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#endif
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if(!bios_reset_detected()) {
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enable_smbus();
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#if 0
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// dump_spd_registers(&memctrl[0]);
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dump_smbus_registers();
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#endif
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memreset_setup();
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sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
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}
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#if 0
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else {
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/* clear memory 1meg */
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__asm__ volatile(
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"1: \n\t"
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"movl %0, %%fs:(%1)\n\t"
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"addl $4,%1\n\t"
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"subl $4,%2\n\t"
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"jnz 1b\n\t"
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:
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: "a" (0), "D" (0), "c" (1024*1024)
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);
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}
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#endif
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_device(PCI_DEV(0, 0, 0));
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#endif
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM2);
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print_debug("TOP_MEM2: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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/*
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#if 0
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ram_check(0x00000000, msr.lo+(msr.hi<<32));
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#else
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#if 0
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// Check 16MB of memory @ 0
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ram_check(0x00000000, 0x01000000);
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#else
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// Check 16MB of memory @ 2GB
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ram_check(0x80000000, 0x81000000);
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#endif
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#endif
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*/
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}
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