268744306a
This patch makes the way to protect flash regions selectable. If you don't want to use ifdtool for modification of flash descriptor, enable the new option. Otherwise, the previous config settings for all mainboards will be retained. Change-Id: I46ec6339008edcc78fe76682eed5714f85354937 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/31639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
83 lines
2.3 KiB
Plaintext
83 lines
2.3 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_INTEL_LYNXPOINT
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bool
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if SOUTHBRIDGE_INTEL_LYNXPOINT
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config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SPI
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select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
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select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
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select IOAPIC
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select HAVE_SMI_HANDLER
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select HAVE_USBDEBUG_OPTIONS
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SPI_CONSOLE_SUPPORT
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select RTC
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select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
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select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
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select HAVE_INTEL_CHIPSET_LOCKDOWN
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select COMMON_FADT
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select HAVE_POWER_STATE_AFTER_FAILURE
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select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
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config INTEL_LYNXPOINT_LP
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bool
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default n
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help
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Set this option to y for Lynxpont LP (Haswell ULT).
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config EHCI_BAR
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hex
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default 0xe8000000
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/lynxpoint/bootblock.c"
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config ME_MBP_CLEAR_LATE
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bool "Defer wait for ME MBP Cleared"
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default y
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help
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If you set this option to y, the Management Engine driver
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will defer waiting for the MBP Cleared indicator until the
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finalize step. This can speed up boot time if the ME takes
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a long time to indicate this status.
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config FINALIZE_USB_ROUTE_XHCI
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bool "Route all ports to XHCI controller in finalize step"
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default y
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help
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If you set this option to y, the USB ports will be routed
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to the XHCI controller during the finalize SMM callback.
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endif
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