2715cdb3f3
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
69 lines
1.6 KiB
Plaintext
69 lines
1.6 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include "variant/ec.h"
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#include "variant/gpio.h"
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/icelake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/icelake/acpi/globalnvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/icelake/acpi/northbridge.asl>
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#include <soc/intel/icelake/acpi/southbridge.asl>
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}
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}
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#if CONFIG(CHROMEOS)
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// Chrome OS specific
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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#endif
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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// Chipset specific sleep states
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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// Mainboard specific
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#include "acpi/mainboard.asl"
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}
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