Jonathan Neuschäfer 27d3402258 arch/riscv: Align trap_entry to 4 bytes, as required by spec ...

The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.

Add the necessary alignment directive before trap_entry.

Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2018-02-20 20:44:43 +00:00

..

arm

Constify struct cpu_device_id instances

2017-11-23 05:00:17 +00:00

arm64

arm64: Add read64() and write64()

2018-02-12 23:05:08 +00:00

mips

Constify struct cpu_device_id instances

2017-11-23 05:00:17 +00:00

power8

Constify struct cpu_device_id instances

2017-11-23 05:00:17 +00:00

riscv

arch/riscv: Align trap_entry to 4 bytes, as required by spec

2018-02-20 20:44:43 +00:00

x86

arch/x86/acpi/statdef.asl: Remove unnecessary whitespace

2018-02-02 16:08:16 +00:00