282171c105
Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <gpio.h>
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uint32_t board_id(void)
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{
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static int id = -1;
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gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
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[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
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if (id < 0) {
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id = gpio_base2_value(pins, ARRAY_SIZE(pins));
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printk(BIOS_SPEW, "Board ID: %d.\n", id);
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}
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return id;
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}
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uint32_t ram_code(void)
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{
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uint32_t code;
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gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
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[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
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code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
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printk(BIOS_SPEW, "RAM Config: %u.\n", code);
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return code;
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}
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