bba53ed1a7
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
68 lines
1.4 KiB
C
68 lines
1.4 KiB
C
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#ifndef RAMINIT_SYSINFO
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#define RAMINIT_SYSINFO 0
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#endif
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static inline void print_debug_sdram_8(const char *strval, uint32_t val)
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{
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#if CONFIG_USE_INIT
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printk_debug("%s%02x\r\n", strval, val);
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#else
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print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
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#endif
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}
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void sdram_no_memory(void)
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{
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print_err("No memory!!\r\n");
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while(1) {
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hlt();
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}
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}
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/* Setup SDRAM */
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#if RAMINIT_SYSINFO == 1
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void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
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#else
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void sdram_initialize(int controllers, const struct mem_controller *ctrl)
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#endif
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{
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int i;
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/* Set the registers we can set once to reasonable values */
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for(i = 0; i < controllers; i++) {
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print_debug_sdram_8("Ram1.",i);
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#if RAMINIT_SYSINFO == 1
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sdram_set_registers(ctrl + i , sysinfo);
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#else
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sdram_set_registers(ctrl + i);
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#endif
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}
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/* Now setup those things we can auto detect */
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for(i = 0; i < controllers; i++) {
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print_debug_sdram_8("Ram2.",i);
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#if RAMINIT_SYSINFO == 1
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sdram_set_spd_registers(ctrl + i , sysinfo);
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#else
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sdram_set_spd_registers(ctrl + i);
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#endif
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}
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/* Now that everything is setup enable the SDRAM.
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* Some chipsets do the work for us while on others
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* we need to it by hand.
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*/
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print_debug("Ram3\r\n");
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#if RAMINIT_SYSINFO == 1
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sdram_enable(controllers, ctrl, sysinfo);
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#else
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sdram_enable(controllers, ctrl);
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#endif
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print_debug("Ram4\r\n");
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}
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