BUG=b:153888802 TEST=Able to list correct PCH revision, SPI/eSPI frequency as per ADL SPI flash guide. Without this CL : PCH Revision: 500 series Tiger Point With this CL : PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
		
			
				
	
	
		
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			190 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/* ifdtool - dump Intel Firmware Descriptor information */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <stdbool.h>
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#define IFDTOOL_VERSION "1.2"
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enum ifd_version {
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	IFD_VERSION_1,
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	IFD_VERSION_2,
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};
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/* port from flashrom */
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enum ich_chipset {
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	CHIPSET_ICH_UNKNOWN,
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	CHIPSET_ICH,
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	CHIPSET_ICH2345,
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	CHIPSET_ICH6,
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	CHIPSET_POULSBO, /* SCH U* */
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	CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
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	CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
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	CHIPSET_ICH7,
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	CHIPSET_ICH8,
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	CHIPSET_ICH9,
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	CHIPSET_ICH10,
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	CHIPSET_PCH_UNKNOWN,
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	CHIPSET_5_SERIES_IBEX_PEAK,
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	CHIPSET_6_SERIES_COUGAR_POINT,
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	CHIPSET_7_SERIES_PANTHER_POINT,
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	CHIPSET_8_SERIES_LYNX_POINT,
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	CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
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			   * Bay Trail, Avoton/Rangeley
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			   */
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	CHIPSET_8_SERIES_LYNX_POINT_LP,
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	CHIPSET_8_SERIES_WELLSBURG,
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	CHIPSET_9_SERIES_WILDCAT_POINT,
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	CHIPSET_9_SERIES_WILDCAT_POINT_LP,
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	CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
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	CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
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	CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */
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	CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
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						   * variants onwards */
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	CHIPSET_C620_SERIES_LEWISBURG,
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};
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enum platform {
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	PLATFORM_APL,
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	PLATFORM_CNL,
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	PLATFORM_GLK,
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	PLATFORM_ICL,
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	PLATFORM_JSL,
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	PLATFORM_SKLKBL,
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	PLATFORM_TGL,
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	PLATFORM_ADL,
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};
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#define LAYOUT_LINELEN 80
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enum spi_frequency {
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	SPI_FREQUENCY_20MHZ = 0,
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	SPI_FREQUENCY_33MHZ = 1,
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	SPI_FREQUENCY_48MHZ = 2,
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	SPI_FREQUENCY_50MHZ_30MHZ = 4,
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	SPI_FREQUENCY_17MHZ = 6,
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};
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enum spi_frequency_500_series {
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	SPI_FREQUENCY_100MHZ = 0,
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	SPI_FREQUENCY_50MHZ = 1,
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	SPI_FREQUENCY_500SERIES_33MHZ = 3,
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	SPI_FREQUENCY_25MHZ = 4,
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	SPI_FREQUENCY_14MHZ = 6,
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};
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enum espi_frequency {
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	ESPI_FREQUENCY_20MHZ = 0,
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	ESPI_FREQUENCY_24MHZ = 1,
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	ESPI_FREQUENCY_30MHZ = 2,
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	ESPI_FREQUENCY_48MHZ = 3,
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	ESPI_FREQUENCY_60MHZ = 4,
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	ESPI_FREQUENCY_17MHZ = 6,
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};
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enum espi_frequency_500_series {
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	ESPI_FREQUENCY_500SERIES_20MHZ = 0,
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	ESPI_FREQUENCY_500SERIES_24MHZ = 1,
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	ESPI_FREQUENCY_500SERIES_25MHZ = 2,
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	ESPI_FREQUENCY_500SERIES_48MHZ = 3,
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	ESPI_FREQUENCY_500SERIES_60MHZ = 4,
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};
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enum component_density {
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	COMPONENT_DENSITY_512KB = 0,
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	COMPONENT_DENSITY_1MB   = 1,
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	COMPONENT_DENSITY_2MB   = 2,
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	COMPONENT_DENSITY_4MB   = 3,
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	COMPONENT_DENSITY_8MB   = 4,
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	COMPONENT_DENSITY_16MB  = 5,
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	COMPONENT_DENSITY_32MB  = 6,
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	COMPONENT_DENSITY_64MB  = 7,
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	COMPONENT_DENSITY_UNUSED = 0xf
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};
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// flash descriptor
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typedef struct {
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	uint32_t flvalsig;
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	uint32_t flmap0;
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	uint32_t flmap1;
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	uint32_t flmap2;
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	uint32_t flmap3; // Exist for 500 series onwards
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} __attribute__((packed)) fdbar_t;
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// regions
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#define MAX_REGIONS 9
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#define MAX_REGIONS_OLD 5
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enum flash_regions {
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	REGION_DESC,
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	REGION_BIOS,
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	REGION_ME,
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	REGION_GBE,
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	REGION_PDR,
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	REGION_EC = 8,
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};
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typedef struct {
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	uint32_t flreg[MAX_REGIONS];
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} __attribute__((packed)) frba_t;
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// component section
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typedef struct {
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	uint32_t flcomp;
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	uint32_t flill;
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	uint32_t flpb;
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} __attribute__((packed)) fcba_t;
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// pch strap
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#define MAX_PCHSTRP 1024
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typedef struct {
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	uint32_t pchstrp[MAX_PCHSTRP];
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} __attribute__((packed)) fpsba_t;
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/*
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 * WR / RD bits start at different locations within the flmstr regs, but
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 * otherwise have identical meaning.
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 */
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#define FLMSTR_WR_SHIFT_V1 24
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#define FLMSTR_WR_SHIFT_V2 20
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#define FLMSTR_RD_SHIFT_V1 16
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#define FLMSTR_RD_SHIFT_V2 8
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// master
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typedef struct {
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	uint32_t flmstr1;
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	uint32_t flmstr2;
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	uint32_t flmstr3;
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	uint32_t flmstr4;
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	uint32_t flmstr5;
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} __attribute__((packed)) fmba_t;
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// processor strap
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typedef struct {
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	uint32_t data[8];
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} __attribute__((packed)) fmsba_t;
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// ME VSCC
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typedef struct {
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	uint32_t jid;
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	uint32_t vscc;
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} vscc_t;
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typedef struct {
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	// Actual number of entries specified in vtl
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	/* FIXME: Rationale for the limit of 8.
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	 *        AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
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	vscc_t entry[8];
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} vtba_t;
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typedef struct {
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	int base, limit, size;
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} region_t;
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struct region_name {
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	const char *pretty;
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	const char *terse;
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	const char *filename;
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	const char *fmapname;
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};
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