28a0a14b5b
When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/cpu.h>
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#include <amdblocks/mca.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/smm.h>
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/amd/microcode.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <types.h>
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_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
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"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
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/* MP and SMM loading initialization */
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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*/
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static void pre_mp_init(void)
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{
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x86_setup_mtrrs_with_detect_no_above_4gb();
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x86_mtrr_check();
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}
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static void post_mp_init(void)
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{
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global_smi_enable();
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apm_control(APM_CNT_SMMINFO);
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
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die_with_post_code(POST_HW_INIT_FAILURE,
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"mp_init_with_smm failed. Halting.\n");
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/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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}
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static void zen_2_3_init(struct device *dev)
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{
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check_mca();
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setup_lapic();
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set_cstate_io_addr();
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amd_update_microcode_from_cbfs();
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}
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static struct device_operations cpu_dev_ops = {
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.init = zen_2_3_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, CEZANNE_A0_CPUID},
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{ 0, 0 },
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};
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static const struct cpu_driver zen_2_3 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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