Files
system76-coreboot/src
Tim Wawrzynczak 291b58f06e soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.

Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-24 11:27:51 +00:00
..
2021-02-18 10:11:24 +00:00