231 lines
8.3 KiB
C
231 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_NC(GPP_C22, NONE), // NC
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PAD_NC(GPP_C23, NONE), // NC
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};
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_NC(GPD0, NONE), // PM_BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE), // NC
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PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
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PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A#
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PAD_NC(GPD7, NONE), // NC
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PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
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PAD_NC(GPD9, NONE), // GPD9_RTD3
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PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC
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PAD_NC(GPD11, NONE), // NC
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/* ------- GPIO Group A ------- */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with pull up
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PAD_NC(GPP_A7, NONE), // TPM_PIRQ#
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with pull-up
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
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PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
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PAD_NC(GPP_A11, NONE), // NC
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PAD_NC(GPP_A12, NONE), // PCH_GPP_A12
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
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PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK
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PAD_NC(GPP_A16, NONE), // NC
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PAD_NC(GPP_A17, NONE), // LIGHT_KB_DET#
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PAD_NC(GPP_A18, NONE), // NC
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PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN
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PAD_NC(GPP_A20, NONE), // NC
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PAD_NC(GPP_A21, NONE), // NC
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PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // PS8338B_SW
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PAD_NC(GPP_A23, NONE), // PS8338B_PCH
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/* ------- GPIO Group B ------- */
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PAD_NC(GPP_B0, NONE), // CORE_VID0
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PAD_NC(GPP_B1, NONE), // CORE_VID1
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PAD_NC(GPP_B2, NONE), // CNVI_WAKE#
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PAD_NC(GPP_B3, NONE), // NC
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PAD_NC(GPP_B4, NONE), // NC
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PAD_NC(GPP_B5, NONE), // NC
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PAD_NC(GPP_B6, NONE), // NC
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ#
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ#
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ#
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PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE#
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
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PAD_NC(GPP_B15, NONE), // NC
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PAD_NC(GPP_B16, NONE), // PCH_GPP_B16
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PAD_NC(GPP_B17, NONE), // PCH_GPP_B17
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PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode
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PAD_NC(GPP_B19, NONE), // NC
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PAD_NC(GPP_B20, NONE), // NC
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PAD_NC(GPP_B21, NONE), // NC
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PAD_NC(GPP_B22, NONE), // PCH_GPP_B22
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PAD_NC(GPP_B23, NONE), // NC
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/* ------- GPIO Group C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR
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PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with pull-up
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PAD_NC(GPP_C3, NONE), // NC
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PAD_NC(GPP_C4, NONE), // NC
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PAD_NC(GPP_C5, NONE), // NC
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PAD_NC(GPP_C6, NONE), // LAN_WAKEUP#
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PAD_NC(GPP_C7, NONE), // NC
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PAD_NC(GPP_C8, NONE), // NC
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_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT
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PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR
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PAD_NC(GPP_C11, NONE), // NC
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PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // GPP_C12_RTD3
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PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // SSD_PWR_DN#
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PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBTA_HRESET
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PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // TBT_PERST_N
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
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PAD_NC(GPP_C18, NONE), // NC
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PAD_NC(GPP_C19, NONE), // SWI
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PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
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PAD_NC(GPP_C22, NONE), // NC
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PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
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/* ------- GPIO Group D ------- */
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PAD_NC(GPP_D0, NONE), // NC
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PAD_NC(GPP_D1, NONE), // NC
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PAD_NC(GPP_D2, NONE), // NC
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PAD_NC(GPP_D3, NONE), // NC
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PAD_NC(GPP_D4, NONE), // NC
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PAD_NC(GPP_D5, NONE), // NC
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PAD_NC(GPP_D6, NONE), // NC
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PAD_NC(GPP_D7, NONE), // NC
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PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // SB_BLON
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_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI#
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PAD_NC(GPP_D10, NONE), // NC
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_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
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PAD_NC(GPP_D12, NONE), // PCH_GPP_D12
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PAD_NC(GPP_D13, NONE), // NC
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PAD_NC(GPP_D14, NONE), // NC
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PAD_NC(GPP_D15, NONE), // NC
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PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // RTD3_3G_PW R_EN
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PAD_NC(GPP_D17, NONE), // NC
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PAD_NC(GPP_D18, NONE), // NC
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA
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PAD_NC(GPP_D21, NONE), // TPM_DET#
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PAD_NC(GPP_D22, NONE), // TPM_TCM_Detect
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PAD_NC(GPP_D23, NONE), // NC
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/* ------- GPIO Group E ------- */
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PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with pull-up
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PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT#
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PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2
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PAD_NC(GPP_E3, NONE), // NC
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PAD_NC(GPP_E4, NONE), // NC
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PAD_NC(GPP_E5, NONE), // NC
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PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2
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PAD_NC(GPP_E7, NONE), // NC
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
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PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK
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PAD_NC(GPP_E10, NONE), // GPP_E10
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PAD_NC(GPP_E11, NONE), // GPP_E11
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PAD_NC(GPP_E12, NONE), // USB_OC#78
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD
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_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI#
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_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI#
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD
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PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA
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PAD_NC(GPP_E22, NONE), // NC
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PAD_NC(GPP_E23, NONE), // NC
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/* ------- GPIO Group F ------- */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_NC(GPP_F1, NONE), // NC
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PAD_NC(GPP_F2, NONE), // NC
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PAD_NC(GPP_F3, NONE), // NC
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT
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PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT
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PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
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PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
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PAD_NC(GPP_F10, NONE), // NC
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PAD_NC(GPP_F11, NONE), // NC
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PAD_NC(GPP_F12, NONE), // NC
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PAD_NC(GPP_F13, NONE), // NC
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PAD_NC(GPP_F14, NONE), // NC
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PAD_NC(GPP_F15, NONE), // NC
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PAD_NC(GPP_F16, NONE), // NC
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PAD_NC(GPP_F17, NONE), // NC
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PAD_NC(GPP_F18, NONE), // NC
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PAD_NC(GPP_F19, NONE), // NC
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PAD_NC(GPP_F20, NONE), // NC
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PAD_NC(GPP_F21, NONE), // NC
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PAD_NC(GPP_F22, NONE), // NC
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PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // A4WP_PRESENT
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/* ------- GPIO Group G ------- */
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PAD_NC(GPP_G0, NONE), // EDP_DET
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PAD_NC(GPP_G1, NONE), // NC
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PAD_NC(GPP_G2, NONE), // NC
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PAD_NC(GPP_G3, NONE), // ASM1543_I_SEL0
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PAD_NC(GPP_G4, NONE), // ASM1543_I_SEL1
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PAD_NC(GPP_G5, NONE), // BOARD_ID
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PAD_NC(GPP_G6, NONE), // NC
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PAD_NC(GPP_G7, NONE), // TBT_Detect
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/* ------- GPIO Group H ------- */
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PAD_NC(GPP_H0, NONE), // NC
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PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST#
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ
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PAD_NC(GPP_H3, NONE), // NC
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PAD_NC(GPP_H4, NONE), // T23
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PAD_NC(GPP_H5, NONE), // T22
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PAD_NC(GPP_H6, NONE), // NC
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PAD_NC(GPP_H7, NONE), // NC
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PAD_NC(GPP_H8, NONE), // NC
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PAD_NC(GPP_H9, NONE), // NC
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PAD_NC(GPP_H10, NONE), // NC
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PAD_NC(GPP_H11, NONE), // NC
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PAD_NC(GPP_H12, NONE), // NC
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PAD_NC(GPP_H13, NONE), // NC
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PAD_NC(GPP_H14, NONE), // G_INT1
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PAD_NC(GPP_H15, NONE), // NC
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PAD_NC(GPP_H16, NONE), // NC
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PAD_NC(GPP_H17, NONE), // NC
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
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PAD_NC(GPP_H19, NONE), // NC
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PAD_NC(GPP_H20, NONE), // NC
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PAD_NC(GPP_H21, NONE), // GPPC_H21
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PAD_NC(GPP_H22, NONE), // TBT_RTD3_PWR_EN_R
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PAD_NC(GPP_H23, NONE), // NC, WIGIG_PEWAKE
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};
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#endif
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#endif
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