29647d97c5
HT_CHAIN_UNITID_BASE HT_CHAIN_END_UNITID_BASE SB_HT_CHAIN_ON_BUS0 SB_HT_CHAIN_UNITID_OFFSET_ONLY MAX_CPUS MAX_PHYSICAL_CPUS ROM_SIZE TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 Also hook up asus/p2b-ds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
147 lines
2.4 KiB
Plaintext
147 lines
2.4 KiB
Plaintext
config BOARD_NVIDIA_L1_2PVV
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bool "l1_2pvv"
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select ARCH_X86
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select CPU_AMD_SOCKET_F
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_MCP55
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select SUPERIO_WINBOND_W83627EHG
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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select HAVE_HARD_RESET
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select LIFT_BSP_APIC_ID
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select K8_REV_F_SUPPORT
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default nvidia/l1_2pvv
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depends on BOARD_NVIDIA_L1_2PVV
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_NVIDIA_L1_2PVV
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_NVIDIA_L1_2PVV
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_NVIDIA_L1_2PVV
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config APIC_ID_OFFSET
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hex
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default 16
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depends on BOARD_NVIDIA_L1_2PVV
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config MEM_TRAIN_SEQ
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int
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default 1
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depends on BOARD_NVIDIA_L1_2PVV
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_NVIDIA_L1_2PVV
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config LB_CKS_RANGE_START
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int
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default 49
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depends on BOARD_NVIDIA_L1_2PVV
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config LB_CKS_RANGE_END
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int
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default 122
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depends on BOARD_NVIDIA_L1_2PVV
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config LB_CKS_LOC
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int
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default 123
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depends on BOARD_NVIDIA_L1_2PVV
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config MAINBOARD_PART_NUMBER
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string
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default "l1_2pvv"
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depends on BOARD_NVIDIA_L1_2PVV
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config PCI_64BIT_PREF_MEM
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config HAVE_FALLBACK_BOOT
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config USE_FALLBACK_IMAGE
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_NVIDIA_L1_2PVV
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config MAX_CPUS
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int
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default 4
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depends on BOARD_NVIDIA_L1_2PVV
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config MAX_PHYSICAL_CPUS
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int
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default 2
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depends on BOARD_NVIDIA_L1_2PVV
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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depends on BOARD_NVIDIA_L1_2PVV
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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depends on BOARD_NVIDIA_L1_2PVV
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config USE_INIT
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config SERIAL_CPU_INIT
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config WAIT_BEFORE_CPUS_INIT
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bool
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default n
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depends on BOARD_NVIDIA_L1_2PVV
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1022
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depends on BOARD_NVIDIA_L1_2PVV
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x2b80
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depends on BOARD_NVIDIA_L1_2PVV
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config IRQ_SLOT_COUNT
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int
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default 11
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depends on BOARD_NVIDIA_L1_2PVV
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