Patrick Georgi 29eeeceb2d toolchain: Add POSTCAR as a stage we have a toolchain for ...

Fixes building vb2lib for postcar. Since postcar is an x86ism, add the
Kconfig options only for x86.

Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29395
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2018-11-08 07:41:32 +00:00

..

acpi

arch/x86: Add common AMD ACPI hardware definitions

2017-11-10 19:15:38 +00:00

arch

toolchain: Add POSTCAR as a stage we have a toolchain for

2018-11-08 07:41:32 +00:00

commonlib

src: Remove unneeded whitespace

2018-10-23 15:52:09 +00:00

console

console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOS

2018-10-18 12:50:41 +00:00

cpu

cpu/amd: Use common AMD's MSR

2018-11-05 09:05:51 +00:00

device

src: Remove unneeded whitespace

2018-10-23 15:52:09 +00:00

drivers

drivers/intel/fsp2_0: Run SplitFspBin with python2

2018-11-07 20:54:55 +00:00

ec

chromeec: Disable battery remaining capacity workaround

2018-11-06 17:38:43 +00:00

include

soc/intel/common: Include Icelake device IDs

2018-11-07 20:57:45 +00:00

lib

src/lib/edid: avoid buffer overflow

2018-11-06 14:07:58 +00:00

mainboard

siemens/mc_apl4: Add new mainboard variant mc_apl4

2018-11-07 20:57:00 +00:00

northbridge

nb/intel/x4x/raminit: Add missing space

2018-11-05 09:16:07 +00:00

security

src: Add missing include <stdint.h>

2018-11-01 11:25:07 +00:00

soc

soc/intel/common: Include Icelake device IDs

2018-11-07 20:57:45 +00:00

southbridge

sb/intel: Deduplicate vbnv_cmos_failed and rtc_init

2018-11-07 18:12:39 +00:00

superio

src: Add missing include <stdint.h>

2018-11-01 11:25:07 +00:00

vendorcode

sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors

2018-11-01 22:24:24 +00:00

Kconfig

reset: Finalize move to new API

2018-10-31 15:29:42 +00:00