2a31fcd6f8
Update flash image size to 16MB and update image layout in flashmap descriptor file. BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16083 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
53 lines
1.5 KiB
Plaintext
53 lines
1.5 KiB
Plaintext
FLASH 16M {
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WP_RO@0x0 0x800000 {
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SI_DESC@0x0 0x1000
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IFWI@0x1000 0x1ff000
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RO_SECTION@0x200000 0x600000 {
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RO_VPD@0x0 0x4000
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FMAP@0x4000 0x800
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RO_FRID@0x4800 0x40
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RO_FRID_PAD@0x4840 0x7c0
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COREBOOT(CBFS)@0x5000 0x17b000
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GBB@0x180000 0x40000
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RO_UNUSED_1@0x1c0000 0x400000
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# logical boot partition 2. Remove with updated CSE
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SIGN_CSE@0x5c0000 0x10000
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RO_UNUSED_2@0x5d0000 0x30000
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}
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}
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MISC_RW@0x800000 0x1a000 {
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RW_MRC_CACHE@0x0 0x10000
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RW_ELOG@0x10000 0x4000
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RW_SHARED@0x14000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x18000 0x2000
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}
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RW_SECTION_A@0x81a000 0x28f800 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x27f7c0
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RW_FWID_A@0x28f7c0 0x40
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}
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RW_SECTION_B@0xaa9800 0x28f800 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x27f7c0
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RW_FWID_B@0x28f7c0 0x40
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}
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RW_NVRAM@0xd39000 0x6000
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RW_LEGACY(CBFS)@0xd3f000 0x200000
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BIOS_UNUSABLE@0xf3f000 0x40000
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DEVICE_EXTENSION@0xf7f000 0x80000
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# Currently, it is required that the BIOS region be a multiple of 8KiB.
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# This is required so that the recovery mechanism can find SIGN_CSE
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# region aligned to 4K at the center of BIOS region. Since the
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# descriptor at the beginning uses 4K and BIOS starts at an offset of
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# 4K, a hole of 4K is created towards the end of the flash to compensate
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# for the size requirement of BIOS region.
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# FIT tool thus creates descriptor with following regions:
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# Descriptor --> 0 to 4K
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# BIOS --> 4K to 0xf7f000
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# Device ext --> 0xf7f000 to 0xfff000
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UNUSED_HOLE@0xfff000 0x1000
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}
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