2ad7ea07b8
This adds all USB ports to the device tree. Additionally, it adds _PS0 and _PS3 ACPI methods for the visible USB A ports, which makes it possible to control the port power (VBUS) of each port individually. Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6 Signed-off-by: Emil Lundmark <lndmrk@chromium.org> Reviewed-on: https://review.coreboot.org/26472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
75 lines
1.3 KiB
Plaintext
75 lines
1.3 KiB
Plaintext
if BOARD_GOOGLE_FIZZ
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_USES_FSP2_0
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select NO_FADT_8042
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select SOC_INTEL_KABYLAKE
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select MAINBOARD_HAS_SPI_TPM_CR50
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select SPI_TPM
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select TPM2
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select GENERIC_SPD_BIN
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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select SPD_READ_BY_WORD
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_EC_EFS
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select VBOOT_PHYSICAL_REC_SWITCH
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select HAS_RECOVERY_MRC_CACHE
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select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
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config DRIVER_TPM_SPI_BUS
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default 0x1
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config GBB_HWID
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string
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depends on CHROMEOS
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default "FIZZ TEST 5997"
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config MAINBOARD_DIR
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string
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default "google/fizz"
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config MAINBOARD_PART_NUMBER
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string
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default "Fizz"
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config MAINBOARD_FAMILY
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string
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default "Google_Fizz"
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config MAX_CPUS
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int
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default 8
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 64 # GPE0_DW2_00 (GPP_E0)
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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select NHLT_RT5663
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endif
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