2b34db8d1d
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801er.h"
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void i82801er_enable(device_t dev)
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{
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device_t lpc_dev;
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unsigned index = 0;
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uint16_t reg_old, reg;
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/* See if we are behind the i82801er pci bridge */
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lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
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if((dev->path.pci.devfn &0xf8)== 0xf8) {
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index = dev->path.pci.devfn & 7;
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}
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else if((dev->path.pci.devfn &0xf8)== 0xe8) {
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index = (dev->path.pci.devfn & 7) +8;
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}
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if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
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return;
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}
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if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
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(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) {
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uint32_t id;
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if (id != (PCI_VENDOR_ID_INTEL |
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(PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) {
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return;
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}
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}
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reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
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reg &= ~(1 << index);
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if (!dev->enabled) {
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reg |= (1 << index);
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}
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if (reg != reg_old) {
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pci_write_config16(lpc_dev, 0xf2, reg);
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}
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}
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struct chip_operations southbridge_intel_i82801er_ops = {
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CHIP_NAME("Intel 82801ER Southbridge")
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.enable_dev = i82801er_enable,
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};
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