2c021383c0
Haswell and Broadwell platforms usually stitch six microcode patches. It has worked so far with the default value of four thanks a bug which is being fixed by `util/ifittool: Error out if microcodes do not fit the FIT table' commit. BUG=b:245380705 TEST=Jenkins build without failing on the FIT table size Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I23bf79a3e8918499f6c51e6ef829312d5872181a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
43 lines
703 B
Plaintext
43 lines
703 B
Plaintext
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config CPU_INTEL_HASWELL
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bool
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if CPU_INTEL_HASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
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select MMX
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select SSE2
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select SUPPORT_CPU_UCODE_IN_CBFS
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#select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select CPU_INTEL_COMMON
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select CPU_INTEL_COMMON_TIMEBASE
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select HAVE_ASAN_IN_ROMSTAGE
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select CPU_INTEL_COMMON_VOLTAGE
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 8
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config CPU_INTEL_NUM_FIT_ENTRIES
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default 6
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endif
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