2c0aa00d6e
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
73 lines
1.7 KiB
Plaintext
73 lines
1.7 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# coreboot config options: southbridge
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408 1 e 10 sata_mode
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409 2 e 7 power_on_after_fail
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411 1 e 1 nmi
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# coreboot config options: cpu
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# coreboot config options: northbridge
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432 4 e 11 gfx_uma_size
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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10 0 AHCI
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10 1 Compatible
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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11 7 128M
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11 8 256M
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11 9 96M
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11 10 160M
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11 11 224M
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11 12 352M
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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