2c482a969a
The reason for hardcoding the position of the MRC cache was to satisfy the alignment to the erase size of the flash chip. Hardcoding is no longer needed, as we can specify alignment directly. In the long term, the MRC cache will have to move to FMAP, but for now, we reduce fragmentation in CBFS. Note that soc/intel/common hardcoding of mrc.cache is not removed, as the mrc cache implementation there does not use CBFS to find the cache region, and needs a hardcoded address. Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
123 lines
3.5 KiB
Plaintext
123 lines
3.5 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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if PLATFORM_USES_FSP1_0
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comment "Intel FSP"
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config HAVE_FSP_BIN
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bool "Use Intel Firmware Support Package"
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help
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Select this option to add an Intel FSP binary to
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the resulting coreboot image.
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Note: Without this binary, coreboot builds relying on the FSP
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will not boot
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x4000
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if HAVE_FSP_BIN
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config FSP_FILE
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string "Intel FSP binary path and filename"
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help
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The path and filename of the Intel FSP binary for this platform.
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config FSP_LOC
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hex "Intel FSP Binary location in CBFS"
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help
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The location in CBFS that the FSP is located. This must match the
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value that is set in the FSP binary. If the FSP needs to be moved,
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rebase the FSP with Intel's BCT (tool).
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config ENABLE_FSP_FAST_BOOT
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bool "Enable Fast Boot"
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select ENABLE_MRC_CACHE
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default n
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help
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Enabling this feature will force the MRC data to be cached in NV
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storage to be used for speeding up boot time on future reboots
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and/or power cycles.
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config ENABLE_MRC_CACHE
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bool
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default y if HAVE_ACPI_RESUME
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default n
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help
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Enabling this feature will cause MRC data to be cached in NV storage.
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This can either be used for fast boot, or just because the FSP wants
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it to be saved.
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config MRC_CACHE_SIZE
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hex "Fast Boot Data Cache Size"
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default 0x10000
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depends on ENABLE_MRC_CACHE
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help
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This is the amount of space in NV storage that is reserved for the
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fast boot data cache storage.
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WARNING: Because this area will be erased and re-written, the size
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should be a full sector of the flash ROM chip and nothing else should
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be included in CBFS in any sector that the fast boot cache data is in.
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config VIRTUAL_ROM_SIZE
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hex "Virtual ROM Size"
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default ROM_SIZE
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depends on ENABLE_MRC_CACHE
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help
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This is used to calculate the offset of the MRC data cache in NV
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Storage for fast boot. If in doubt, leave this set to the default
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which sets the virtual size equal to the ROM size.
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Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
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loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
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the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
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size is 16 MB.
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endif #HAVE_FSP_BIN
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config CACHE_ROM_SIZE_OVERRIDE
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hex "Cache ROM Size"
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default CBFS_SIZE
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help
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This is the size of the cachable area that is passed into the FSP in
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the early initialization. Typically this should be the size of the CBFS
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area, but the size must be a power of 2 whereas the CBFS size does not
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have this limitation.
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config USE_GENERIC_FSP_CAR_INC
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bool
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default n
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help
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The chipset can select this to use a generic cache_as_ram.inc file
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that should be good for all FSP based platforms.
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config FSP_USES_UPD
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bool
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default n
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help
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If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
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endif #PLATFORM_USES_FSP1_0
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