2cb399625e
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <bootmode.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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/* Write Protect: GPIO22 */
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{0, ACTIVE_LOW, !get_write_protect_state(), "write protect"},
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/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
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{69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
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/* Hard code the lid switch GPIO to open. */
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{-1, ACTIVE_HIGH, 1, "lid"},
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/* Power Button */
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{-1, ACTIVE_HIGH, 0, "power"},
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/* Did we load the VGA option ROM? */
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#endif
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int get_recovery_mode_switch(void)
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{
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/*
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* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
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* J8E2. The jump is active high.
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*/
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return get_gpio(69);
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}
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int get_write_protect_state(void)
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{
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/* Write protect is active low, so invert it here */
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return !get_gpio(22);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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