20a87c0bed
Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
21 lines
627 B
C
21 lines
627 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <libpayload.h>
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#include <pci.h>
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#define PCIE_CFGNUM_REG 0x140
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#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
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#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
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#define PCIE_CFG_OFFSET_ADDR 0x1000
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#define PCIE_CFG_HEADER(bus, devfn) \
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(PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
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uintptr_t pci_map_bus(pcidev_t dev)
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{
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u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
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u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn);
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write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val);
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return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR;
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}
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