2cf9d3883c
Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
60 lines
1.3 KiB
Plaintext
60 lines
1.3 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/itss.h>
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#include <intelblocks/pcr.h>
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#include <soc/itss.h>
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#include <soc/pcr_ids.h>
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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/* PCH clock */
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#include "camera_clock_ctl.asl"
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/* GPIO controller */
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#include "gpio.asl"
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/* ESPI 0:1f.0 */
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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/* PCH HDA */
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#include "pch_hda.asl"
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/* PCIE Ports */
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#include "pcie.asl"
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/* pmc 0:1f.2 */
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#include "pmc.asl"
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/* Serial IO */
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#include "serialio.asl"
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/* SMBus 0:1f.4 */
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#include "smbus.asl"
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/* ISH 0:12.0 */
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#include "ish.asl"
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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