2d0aaa7fc1
Rework display_fsp_smbios_memory_info_hob (shared code). Import code to convert memory HOB to dimm info for SMBIOS table 17 mostly copied from fsp1_1 mainboard_save_dimm_info. Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23851 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
96 lines
3.0 KiB
Makefile
96 lines
3.0 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 - 2017 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-$(CONFIG_FSP_CAR)+= bootblock/cache_as_ram_fsp.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_CONSOLE_SERIAL) += bootblock/uart.c
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bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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postcar-y += memmap.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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postcar-y += spi.c
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postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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romstage-y += memmap.c
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romstage-y += reset.c
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romstage-y += romstage.c
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romstage-y += tsc_freq.c
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romstage-y += gpio.c
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romstage-y += soc_util.c
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romstage-y += spi.c
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romstage-y += fiamux.c
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romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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ramstage-y += memmap.c
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ramstage-y += systemagent.c
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ramstage-y += reset.c
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ramstage-y += chip.c
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ramstage-y += soc_util.c
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ramstage-y += uart.c
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ramstage-y += xhci.c
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ramstage-y += csme_ie_kt.c
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ramstage-y += lpc.c
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ramstage-y += pmc.c
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ramstage-y += npk.c
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ramstage-y += sata.c
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ramstage-y += cpu.c
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ramstage-y += tsc_freq.c
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ramstage-y += spi.c
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ramstage-y += fiamux.c
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ramstage-y += hob_mem.c
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ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
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ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_util.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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verstage-y += memmap.c
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verstage-y += reset.c
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verstage-y += spi.c
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verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
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CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/denverton_ns
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##Set FSP binary blobs memory location
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$(CONFIG_FSP_T_CBFS)-options := -b $(CONFIG_FSP_T_ADDR) --xip
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$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) --xip
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$(CONFIG_FSP_S_CBFS)-options := -b $(CONFIG_FSP_S_ADDR) --xip
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endif ## CONFIG_SOC_INTEL_DENVERTON_NS
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