2d4986c168
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
77 lines
1.7 KiB
Makefile
77 lines
1.7 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += gspi.c
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all-y += i2c.c
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all-y += pmutil.c
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all-y += spi.c
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all-y += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += dptf.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += graphics.c
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ramstage-y += lockdown.c
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ramstage-y += lpm.c
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ramstage-y += me.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += soundwire.c
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ramstage-y += systemagent.c
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ramstage-y += xhci.c
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ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog_lib.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += elog.c
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smm-y += xhci.c
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ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y)
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bootblock-y += gpio_pch_h.c
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romstage-y += gpio_pch_h.c
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ramstage-y += gpio_pch_h.c
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smm-y += gpio_pch_h.c
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verstage-y += gpio_pch_h.c
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else
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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smm-y += gpio.c
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verstage-y += gpio.c
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
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ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_PCH_H),y)
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8d-01
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else
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-01
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-02
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endif
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endif
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