2d7173d462
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
137 lines
2.8 KiB
C
137 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/x86/smm.h>
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#include <cpu/intel/smm_reloc.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "pmutil.h"
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#define DEBUG_PERIODIC_SMIS 0
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u16 get_pmbase(void)
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{
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return lpc_get_pmbase();
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}
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void smm_southbridge_enable_smi(void)
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{
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u32 smi_en;
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u16 pm1_en;
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u32 gpe0_en;
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if (CONFIG(ELOG))
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/* Log events from chipset before clearing */
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pch_log_state();
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printk(BIOS_DEBUG, "Initializing southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase());
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smi_en = read_pmbase32(SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Disable GPE0 PME_B0 */
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gpe0_en = read_pmbase32(GPE0_EN);
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gpe0_en &= ~PME_B0_EN;
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write_pmbase32(GPE0_EN, gpe0_en);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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write_pmbase16(PM1_EN, pm1_en);
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/* Enable SMI generation:
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* - on TCO events
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on microcontroller writes (io 0x62/0x66)
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*/
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smi_en = 0; /* reset SMI enables */
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#if 0
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smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
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#endif
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
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* periodic SMIs.
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*/
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smi_en |= PERIODIC_EN;
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#endif
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smi_en |= SLP_SMI_EN;
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#if 0
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smi_en |= BIOS_EN;
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#endif
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/* The following need to be on for SMIs to happen */
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smi_en |= EOS | GBL_SMI_EN;
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write_pmbase32(SMI_EN, smi_en);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((uintptr_t)gnvs),
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"d" (APM_CNT)
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);
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}
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void smm_southbridge_clear_state(void)
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{
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u32 smi_en;
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if (CONFIG(ELOG))
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/* Log events from chipset before clearing */
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pch_log_state();
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
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smi_en = inl(get_pmbase() + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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printk(BIOS_DEBUG, "\n");
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/* Dump and clear status registers */
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reset_smi_status();
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reset_pm1_status();
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reset_tco_status();
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reset_gpe0_status();
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}
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