2dd3f877cc
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
74 lines
2.5 KiB
Makefile
74 lines
2.5 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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## Copyright (C) 2013 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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ifeq ($(CONFIG_INCLUDE_ME),y)
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INTERMEDIATE+=bd82x6x_add_me
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endif
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ramstage-y += pch.c
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ramstage-y += azalia.c
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ramstage-y += lpc.c
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ramstage-y += sata.c
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ramstage-y += me.c
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ramstage-y += me_8.x.c
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ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += ../common/spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
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smm-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-y += reset.c
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romstage-y += early_spi.c
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bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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PHONY += bd82x6x_add_me
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INCLUDES += -I$(src)/southbridge/intel/fsp_bd82x6x
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