2e1fea408d
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
31 lines
1016 B
C
31 lines
1016 B
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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* Copyright (C) 2018 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H
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#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H
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#include <arch/io.h>
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#include <device/pnp_type.h>
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#include <stdint.h>
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void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase);
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void pnp_enter_conf_state(pnp_devfn_t dev);
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void pnp_exit_conf_state(pnp_devfn_t dev);
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#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */
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