2e2fe3cc91
Set GPP_B4 to low in S5 to meet touch panel power sequence BUG=b:124197348 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
42 lines
1.0 KiB
C
42 lines
1.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/smm.h>
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#include <soc/smm.h>
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#include <baseboard/variants.h>
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#include <variant/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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chromeec_smi_process_events();
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}
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void __weak variant_smi_sleep(u8 slp_typ) {}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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variant_smi_sleep(slp_typ);
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
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MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, 0);
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return 0;
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}
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