Xiang Wang 2e38dbe5f1 riscv: update mtime initialization ...

Add a interface, which is implemented by SoC.

Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

2018-09-10 15:03:08 +00:00

..

arm

src/arch: Fix typo

2018-08-09 15:56:02 +00:00

arm64

arm64: Factor out common parts of romstage execution flow

2018-08-17 21:29:46 +00:00

mips

arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)

2018-08-07 20:55:58 +00:00

power8

arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)

2018-08-07 20:55:58 +00:00

riscv

riscv: update mtime initialization

2018-09-10 15:03:08 +00:00

x86

x86/acpi: Add BERT table

2018-09-07 14:50:34 +00:00