2ee5c9e21b
the possible IRQs generated by the SIO. This included IRQ 7 as the default parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards that were setting it to prevent the conflict and crash when the MFGPT driver loads. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
149 lines
4.8 KiB
Plaintext
149 lines
4.8 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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if USE_DCACHE_RAM
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# Compile cache_as_ram.c to auto.inc.
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makerule ./cache_as_ram_auto.inc
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# depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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depends "$(MAINBOARD)/cache_as_ram_auto.c"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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# mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/model_lx/cache_as_ram.inc
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mainboardinit ./cache_as_ram_auto.inc
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end
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dir /pc80
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config chip.h
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
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register "lpc_serirq_enable" = "0x0000105a"
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register "lpc_serirq_polarity" = "0x0000EFA5"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "1" # 0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "0"
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register "com1_address" = "0x3F8"
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register "com1_irq" = "4"
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register "com2_enable" = "0"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci 9.0 on end # Slot1
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device pci a.0 on end # Slot2
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device pci b.0 on end # Slot3
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device pci c.0 on end # Slot4
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device pci e.0 on end # Ethernet 0
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device pci 10.0 on end # Ethernet 1
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device pci 11.0 on end # SATA
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device pci f.0 on # ISA Bridge
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b off end # HW Monitor
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end
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end
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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end
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end
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end
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