2f2e63bc7d
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
90 lines
3.4 KiB
INI
Executable File
90 lines
3.4 KiB
INI
Executable File
; bdiGDB configuration file for the Embedded Planet EP405PC
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; ---------------------------------------------------------
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;
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[INIT]
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; init core register
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WSPR 954 0x00000000 ;DCWR: Disable data cache write-thru
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WSPR 1018 0x00000000 ;DCCR: Disable data cache
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WSPR 1019 0x00000000 ;ICCR: Disable instruction cache
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WSPR 981 0x00000000 ;EVPR: Exception Vector Table @0x00000000
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; Setup SDRAM Controller
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WDCR 16 0x00000080 ;Select SDRAM0_TR
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WDCR 17 0x010E8016 ;TR: SDRAM Timing Register
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WDCR 16 0x00000040 ;Select SDRAM0_B0CR
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WDCR 17 0x00084001 ;Select bank 0
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WDCR 16 0x00000030 ;Select SDRAM0_RTR
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WDCR 17 0x08080000 ;RTR: Refresh Timing Register
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WDCR 16 0x00000094 ;Select SDRAM0_ECCCFG
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WDCR 17 0x00000000 ;ECC: Disabled
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WDCR 16 0x00000034 ;Select SDRAM0_PMIT
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WDCR 17 0x0F000000 ;PMIT: Power Management Idle Timer
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DELAY 1 ;Wait for SDRAM powerup
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WDCR 16 0x00000020 ;Select SDRAM0_CFG
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WDCR 17 0x80C00000 ;CFG: Enable
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; MMU
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WM32 0xf0 0x00000000 ;invalidate page table base
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; EBC
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WDCR 0x12 0x00000004 ;Select EBC0_B4CR
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WDCR 0x13 0xF4058000 ;Set NVRTC/BCSR
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WDCR 0x12 0x00000014 ;Select EBC0_B4AP
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WDCR 0x13 0x04050000 ;Set NVRTC/BCSR timing
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WM8 0xF4000003 0x20 ;Enable UART0
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WM8 0xF4000009 0x07 ;LED
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DELAY 500
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WM8 0xF4000009 0x0b ;LED
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DELAY 500
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WM8 0xF4000009 0x0d ;LED
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DELAY 500
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WM8 0xF4000009 0x0e ;LED
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DELAY 500
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[TARGET]
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JTAGCLOCK 0 ;use 16 MHz JTAG clock
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CPUTYPE 405 ;the used target CPU type
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BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT)
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;WAKEUP 3000 ;wakeup time after reset
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BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
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STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints
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VECTOR CATCH ;catch unhandled exceptions
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MMU XLAT 0xC0000000 ;enable virtual address mode
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PTBASE 0x000000f0 ;address where kernel/user stores pointer to page table
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SIO 2002 9600 ;TCP port for serial IO
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;SIO 2002 115200 ;TCP port for serial IO
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;REGLIST SPR ;select register to transfer to GDB
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;REGLIST ALL ;select register to transfer to GDB
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;SCANPRED 2 2 ;JTAG devices connected before PPC400
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;SCANSUCC 3 3 ;JTAG devices connected after PPC400
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[HOST]
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IP 10.0.1.2
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FORMAT ELF
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FILE linuxbios.elf
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;START 0x200000
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LOAD MANUAL ;load code MANUAL or AUTO after reset
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DEBUGPORT 2001
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DUMP dump.bin ;Linux: dump.bin must already exist and public writable
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[FLASH]
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WORKSPACE 0x00004000 ;workspace in target RAM for fast programming algorithm
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CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
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CHIPSIZE 0x400000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
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BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32)
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ERASE 0xFFF80000 ;erase sector 0 of flash in U7 (AM29F040)
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ERASE 0xFFF90000 ;erase sector 1 of flash
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ERASE 0xFFFA0000 ;erase sector 2 of flash
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ERASE 0xFFFB0000 ;erase sector 3 of flash
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ERASE 0xFFFC0000 ;erase sector 4 of flash
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ERASE 0xFFFD0000 ;erase sector 5 of flash
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ERASE 0xFFFE0000 ;erase sector 6 of flash
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ERASE 0xFFFF0000 ;erase sector 7 of flash
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[REGS]
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IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA
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IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA
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IDCR3 0x014 0x015 ;KIAR and KIDR
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FILE reg405gp.def
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