`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
221 lines
5.6 KiB
C
221 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/mmio.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <amdblocks/acpimmio.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <soc/i2c.h>
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#include "chip.h"
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/* Global to provide access to chip.c */
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const char *i2c_acpi_name(const struct device *dev);
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static const uintptr_t i2c_bus_address[] = {
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APU_I2C2_BASE,
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APU_I2C3_BASE,
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APU_I2C4_BASE, /* slave device only */
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};
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uintptr_t dw_i2c_base_address(unsigned int bus)
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{
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if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS)
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return 0;
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return i2c_bus_address[bus - APU_I2C_MIN_BUS];
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}
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const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
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{
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const struct soc_amd_picasso_config *config;
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if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS)
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return NULL;
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/* config is not NULL; if it was, config_of_soc calls die() internally */
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config = config_of_soc();
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return &config->i2c[bus];
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}
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const char *i2c_acpi_name(const struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case APU_I2C2_BASE:
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return "I2C2";
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case APU_I2C3_BASE:
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return "I2C3";
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case APU_I2C4_BASE:
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return "I2C4";
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default:
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return NULL;
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}
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}
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int dw_i2c_soc_dev_to_bus(struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case APU_I2C2_BASE:
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return 2;
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case APU_I2C3_BASE:
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return 3;
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case APU_I2C4_BASE:
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return 4;
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}
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return -1;
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}
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__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { }
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static void dw_i2c_soc_init(bool is_early_init)
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{
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size_t i;
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const struct soc_amd_picasso_config *config;
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uint32_t pad_ctrl;
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int misc_reg;
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/* config is not NULL; if it was, config_of_soc calls die() internally */
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config = config_of_soc();
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for (i = 0; i < ARRAY_SIZE(config->i2c); i++) {
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const struct dw_i2c_bus_config *cfg = &config->i2c[i];
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if (cfg->early_init != is_early_init)
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continue;
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if (dw_i2c_init(i, cfg)) {
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printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i);
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continue;
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}
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misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * i;
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pad_ctrl = misc_read32(misc_reg);
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pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK;
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pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL;
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pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK;
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pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V;
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pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK;
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pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD
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? I2C_PAD_CTRL_FALLSLEW_STD
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: I2C_PAD_CTRL_FALLSLEW_LOW;
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pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN;
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mainboard_i2c_override(i, &pad_ctrl);
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misc_write32(misc_reg, pad_ctrl);
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}
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}
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void i2c_soc_early_init(void)
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{
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dw_i2c_soc_init(true);
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}
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void i2c_soc_init(void)
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{
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dw_i2c_soc_init(false);
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}
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struct device_operations picasso_i2c_mmio_ops = {
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/* TODO(teravest): Move I2C resource info here. */
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.scan_bus = scan_smbus,
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.acpi_name = i2c_acpi_name,
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.acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt,
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};
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/*
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* I2C pins are open drain with external pull up, so in order to bit bang them
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* all, SCL pins must become GPIO inputs with no pull, then they need to be
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* toggled between input-no-pull and output-low. This table is for the initial
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* conversion of all SCL pins to input with no pull.
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*/
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static const struct soc_amd_gpio i2c_2_gpi[] = {
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PAD_GPI(I2C2_SCL_PIN, PULL_NONE),
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PAD_GPI(I2C3_SCL_PIN, PULL_NONE),
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/* I2C4 is a slave device only */
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};
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#define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
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/*
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* To program I2C pins without destroying their programming, the registers
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* that will be changed need to be saved first.
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*/
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static void save_i2c_pin_registers(uint8_t gpio,
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struct soc_amd_i2c_save *save_table)
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{
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uint32_t *gpio_ptr;
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gpio_ptr = (uint32_t *)gpio_get_address(gpio);
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save_table->mux_value = iomux_read8(gpio);
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save_table->control_value = read32(gpio_ptr);
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}
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static void restore_i2c_pin_registers(uint8_t gpio,
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struct soc_amd_i2c_save *save_table)
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{
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uint32_t *gpio_ptr;
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gpio_ptr = (uint32_t *)gpio_get_address(gpio);
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iomux_write8(gpio, save_table->mux_value);
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iomux_read8(gpio);
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write32(gpio_ptr, save_table->control_value);
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read32(gpio_ptr);
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}
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/* Slaves to be reset are controlled by devicetree register i2c_scl_reset */
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void sb_reset_i2c_slaves(void)
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{
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const struct soc_amd_picasso_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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struct soc_amd_i2c_save save_table[saved_pins_count];
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uint8_t i, j, control;
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if (!dev || !dev->chip_info)
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return;
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cfg = dev->chip_info;
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control = cfg->i2c_scl_reset & GPIO_I2C_MASK;
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if (control == 0)
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return;
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/* Save and reprogram I2C SCL pins */
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for (i = 0; i < saved_pins_count; i++)
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save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
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program_gpios(i2c_2_gpi, saved_pins_count);
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/*
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* Toggle SCL back and forth 9 times under 100KHz. A single read is
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* needed after the writes to force the posted write to complete.
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*/
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for (j = 0; j < 9; j++) {
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if (control & GPIO_I2C2_SCL)
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write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW);
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if (control & GPIO_I2C3_SCL)
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write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW);
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read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
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udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
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if (control & GPIO_I2C2_SCL)
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write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH);
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if (control & GPIO_I2C3_SCL)
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write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH);
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read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */
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udelay(4);
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}
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/* Restore I2C pins. */
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for (i = 0; i < saved_pins_count; i++)
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restore_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]);
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}
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