df5b83fe2b
Refining some of the code indentations and cosmetics to build upon and import some in-review changes. Change-Id: I0038a146bd899f150518c4832258a42792abaabb Signed-off-by: Maximilian Schander <maxschander@googlemail.com> Reviewed-on: https://review.coreboot.org/22216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
205 lines
6.8 KiB
C
205 lines
6.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdio.h>
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#include "me.h"
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
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/* HFS1[3:0] Current Working State Values */
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static const char *me_cws_values[] = {
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[ME_HFS_CWS_RESET] = "Reset",
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[ME_HFS_CWS_INIT] = "Initializing",
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[ME_HFS_CWS_REC] = "Recovery",
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[ME_HFS_CWS_NORMAL] = "Normal",
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[ME_HFS_CWS_WAIT] = "Platform Disable Wait",
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[ME_HFS_CWS_TRANS] = "OP State Transition",
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[ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
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};
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/* HFS1[8:6] Current Operation State Values */
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static const char *me_opstate_values[] = {
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[ME_HFS_STATE_PREBOOT] = "Preboot",
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[ME_HFS_STATE_M0_UMA] = "M0 with UMA",
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[ME_HFS_STATE_M3] = "M3 without UMA",
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[ME_HFS_STATE_M0] = "M0 without UMA",
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[ME_HFS_STATE_BRINGUP] = "Bring up",
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[ME_HFS_STATE_ERROR] = "M0 without UMA but with error"
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};
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/* HFS[19:16] Current Operation Mode Values */
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static const char *me_opmode_values[] = {
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[ME_HFS_MODE_NORMAL] = "Normal",
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[ME_HFS_MODE_DEBUG] = "Debug",
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[ME_HFS_MODE_DIS] = "Soft Temporary Disable",
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[ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper",
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[ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message"
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};
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/* HFS[15:12] Error Code Values */
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static const char *me_error_values[] = {
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[ME_HFS_ERROR_NONE] = "No Error",
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[ME_HFS_ERROR_UNCAT] = "Uncategorized Failure",
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[ME_HFS_ERROR_IMAGE] = "Image Failure",
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[ME_HFS_ERROR_DEBUG] = "Debug Failure"
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};
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/* GMES[31:28] ME Progress Code */
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static const char *me_progress_values[] = {
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[ME_GMES_PHASE_ROM] = "ROM Phase",
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[ME_GMES_PHASE_BUP] = "BUP Phase",
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[ME_GMES_PHASE_UKERNEL] = "uKernel Phase",
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[ME_GMES_PHASE_POLICY] = "Policy Module",
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[ME_GMES_PHASE_MODULE] = "Module Loading",
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[ME_GMES_PHASE_UNKNOWN] = "Unknown",
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[ME_GMES_PHASE_HOST] = "Host Communication"
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};
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/* GMES[27:24] Power Management Event */
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static const char *me_pmevent_values[] = {
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[0x00] = "Clean Moff->Mx wake",
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[0x01] = "Moff->Mx wake after an error",
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[0x02] = "Clean global reset",
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[0x03] = "Global reset after an error",
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[0x04] = "Clean Intel ME reset",
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[0x05] = "Intel ME reset due to exception",
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[0x06] = "Pseudo-global reset",
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[0x07] = "S0/M0->Sx/M3",
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[0x08] = "Sx/M3->S0/M0",
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[0x09] = "Non-power cycle reset",
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[0x0a] = "Power cycle reset through M3",
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[0x0b] = "Power cycle reset through Moff",
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[0x0c] = "Sx/Mx->Sx/Moff"
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};
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/* Progress Code 0 states */
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static const char *me_progress_rom_values[] = {
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[0x00] = "BEGIN",
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[0x06] = "DISABLE"
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};
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/* Progress Code 1 states */
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static const char *me_progress_bup_values[] = {
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[0x00] = "Initialization starts",
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[0x01] = "Disable the host wake event",
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[0x04] = "Flow determination start process",
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[0x08] = "Error reading/matching the VSCC table in the descriptor",
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[0x0a] = "Check to see if straps say ME DISABLED",
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[0x0b] = "Timeout waiting for PWROK",
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[0x0d] = "Possibly handle BUP manufacturing override strap",
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[0x11] = "Bringup in M3",
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[0x12] = "Bringup in M0",
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[0x13] = "Flow detection error",
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[0x15] = "M3 clock switching error",
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[0x18] = "M3 kernel load",
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[0x1c] = "T34 missing - cannot program ICC",
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[0x1f] = "Waiting for DID BIOS message",
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[0x20] = "Waiting for DID BIOS message failure",
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[0x21] = "DID reported an error",
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[0x22] = "Enabling UMA",
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[0x23] = "Enabling UMA error",
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[0x24] = "Sending DID Ack to BIOS",
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[0x25] = "Sending DID Ack to BIOS error",
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[0x26] = "Switching clocks in M0",
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[0x27] = "Switching clocks in M0 error",
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[0x28] = "ME in temp disable",
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[0x32] = "M0 kernel load",
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};
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/* Progress Code 3 states */
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static const char *me_progress_policy_values[] = {
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[0x00] = "Entery into Policy Module",
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[0x03] = "Received S3 entry",
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[0x04] = "Received S4 entry",
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[0x05] = "Received S5 entry",
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[0x06] = "Received UPD entry",
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[0x07] = "Received PCR entry",
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[0x08] = "Received NPCR entry",
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[0x09] = "Received host wake",
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[0x0a] = "Received AC<>DC switch",
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[0x0b] = "Received DRAM Init Done",
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[0x0c] = "VSCC Data not found for flash device",
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[0x0d] = "VSCC Table is not valid",
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[0x0e] = "Flash Partition Boundary is outside address space",
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[0x0f] = "ME cannot access the chipset descriptor region",
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[0x10] = "Required VSCC values for flash parts do not match",
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};
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void intel_me_status(uint32_t hfs, uint32_t gmes)
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{
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/* Check Current States */
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printf("ME: FW Partition Table : %s\n",
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((hfs & 0x20) >> 5) ? "BAD" : "OK");
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printf("ME: Bringup Loader Failure : %s\n",
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((hfs & 0x400) >> 10) ? "YES" : "NO");
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printf("ME: Firmware Init Complete : %s\n",
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((hfs & 0x200) >> 9) ? "YES" : "NO");
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printf("ME: Manufacturing Mode : %s\n",
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((hfs & 0x10) >> 4) ? "YES" : "NO");
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printf("ME: Boot Options Present : %s\n",
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((hfs & 0x1000000) >> 24) ? "YES" : "NO");
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printf("ME: Update In Progress : %s\n",
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((hfs & 0x800) >> 11) ? "YES" : "NO");
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printf("ME: Current Working State : %s\n",
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me_cws_values[hfs & 0xf]);
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printf("ME: Current Operation State : %s\n",
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me_opstate_values[(hfs & 0x1c0) >> 6]);
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printf("ME: Current Operation Mode : %s\n",
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me_opmode_values[(hfs & 0xf0000) >> 16]);
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printf("ME: Error Code : %s\n",
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me_error_values[(hfs & 0xf000) >> 12]);
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printf("ME: Progress Phase : %s\n",
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me_progress_values[(gmes & 0xf0000000) >> 28]);
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printf("ME: Power Management Event : %s\n",
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me_pmevent_values[(gmes & 0xf000000) >> 24]);
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printf("ME: Progress Phase State : ");
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switch ((gmes & 0xf0000000) >> 28) {
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case ME_GMES_PHASE_ROM: /* ROM Phase */
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printf("%s", me_progress_rom_values[(gmes & 0xff0000) >> 16]);
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break;
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case ME_GMES_PHASE_BUP: /* Bringup Phase */
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if ((gmes & 0xff0000) >> 16 < ARRAY_SIZE(me_progress_bup_values)
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&& me_progress_bup_values[(gmes & 0xff0000) >> 16])
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printf("%s",
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me_progress_bup_values[(gmes & 0xff0000) >> 16]);
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else
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printf("0x%02x", (gmes & 0xff0000) >> 16);
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break;
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case ME_GMES_PHASE_POLICY: /* Policy Module Phase */
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if ((gmes & 0xff0000) >> 16 < ARRAY_SIZE(me_progress_policy_values)
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&& me_progress_policy_values[(gmes & 0xff0000) >> 16])
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printf("%s",
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me_progress_policy_values[(gmes & 0xff0000) >> 16]);
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else
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printf("0x%02x", (gmes & 0xff0000) >> 16);
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break;
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case ME_GMES_PHASE_HOST: /* Host Communication Phase */
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if (!((gmes & 0xff0000) >> 16))
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printf("Host communication established");
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else
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printf("0x%02x", (gmes & 0xff0000) >> 16);
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break;
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default:
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printf("Unknown 0x%02x", (gmes & 0xff0000) >> 16);
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}
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printf("\n");
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}
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