315d3264b6
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 2
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/soc_chip.h>
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void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
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{
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const config_t *config = config_of_soc();
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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#if ENV_RAMSTAGE
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void lpc_soc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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pch_misc_init();
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/* Enable CLKRUN_EN for power gating ESPI */
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lpc_enable_pci_clk_cntl();
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/* Set ESPI Serial IRQ mode */
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if (CONFIG(SERIRQ_CONTINUOUS_MODE))
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lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
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else
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lpc_set_serirq_mode(SERIRQ_QUIET);
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/* Interrupt configuration */
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pch_enable_ioapic();
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pch_pirq_init();
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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}
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#endif
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