32471729d9
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/*
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* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree.
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*/
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <stdint.h>
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#include <fsp_util.h>
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#include <soc/pci_devs.h>
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#define SVID_CONFIG1 1
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#define SVID_CONFIG3 3
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struct soc_intel_braswell_config {
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uint8_t enable_xdp_tap;
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uint8_t clkreq_enable;
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/* Disable SLP_X stretching after SUS power well loss. */
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int disable_slp_x_stretch_sus_fail;
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int emmc_acpi_mode;
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int sd_acpi_mode;
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int lpe_acpi_mode;
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/* Allow PCIe devices to wake system from suspend. */
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int pcie_wake_enable;
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during
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* MemoryInit.
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*/
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UINT16 PcdMrcInitTsegSize;
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UINT16 PcdMrcInitMmioSize;
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UINT8 PcdMrcInitSpdAddr1;
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UINT8 PcdMrcInitSpdAddr2;
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UINT8 PcdIgdDvmt50PreAlloc;
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UINT8 PcdApertureSize;
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UINT8 PcdGttSize;
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UINT8 PcdLegacySegDecode;
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during
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* SiliconInit.
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*/
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UINT8 PcdSdcardMode;
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UINT8 PcdEnableHsuart0;
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UINT8 PcdEnableHsuart1;
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UINT8 PcdEnableAzalia;
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UINT32 AzaliaConfigPtr;
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UINT8 PcdEnableSata;
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UINT8 PcdEnableXhci;
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UINT8 PcdEnableLpe;
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UINT8 PcdEnableDma0;
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UINT8 PcdEnableDma1;
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UINT8 PcdEnableI2C0;
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UINT8 PcdEnableI2C1;
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UINT8 PcdEnableI2C2;
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UINT8 PcdEnableI2C3;
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UINT8 PcdEnableI2C4;
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UINT8 PcdEnableI2C5;
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UINT8 PcdEnableI2C6;
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UINT32 PcdGraphicsConfigPtr;
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UINT8 PunitPwrConfigDisable;
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UINT8 ChvSvidConfig;
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UINT8 DptfDisable;
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UINT8 PcdEmmcMode;
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UINT8 PcdUsb3ClkSsc;
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UINT8 PcdDispClkSsc;
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UINT8 PcdSataClkSsc;
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UINT8 Usb2Port0PerPortPeTxiSet;
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UINT8 Usb2Port0PerPortTxiSet;
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UINT8 Usb2Port0IUsbTxEmphasisEn;
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UINT8 Usb2Port0PerPortTxPeHalf;
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UINT8 Usb2Port1PerPortPeTxiSet;
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UINT8 Usb2Port1PerPortTxiSet;
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UINT8 Usb2Port1IUsbTxEmphasisEn;
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UINT8 Usb2Port1PerPortTxPeHalf;
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UINT8 Usb2Port2PerPortPeTxiSet;
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UINT8 Usb2Port2PerPortTxiSet;
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UINT8 Usb2Port2IUsbTxEmphasisEn;
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UINT8 Usb2Port2PerPortTxPeHalf;
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UINT8 Usb2Port3PerPortPeTxiSet;
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UINT8 Usb2Port3PerPortTxiSet;
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UINT8 Usb2Port3IUsbTxEmphasisEn;
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UINT8 Usb2Port3PerPortTxPeHalf;
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UINT8 Usb2Port4PerPortPeTxiSet;
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UINT8 Usb2Port4PerPortTxiSet;
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UINT8 Usb2Port4IUsbTxEmphasisEn;
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UINT8 Usb2Port4PerPortTxPeHalf;
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UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
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UINT8 PcdSataInterfaceSpeed;
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UINT8 PcdPchUsbSsicPort;
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UINT8 PcdPchUsbHsicPort;
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UINT8 PcdPcieRootPortSpeed;
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UINT8 PcdPchSsicEnable;
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UINT32 PcdLogoPtr;
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UINT32 PcdLogoSize;
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UINT8 PcdRtcLock;
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UINT8 PMIC_I2CBus;
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UINT8 ISPEnable;
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UINT8 ISPPciDevConfig;
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};
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extern struct chip_operations soc_intel_braswell_ops;
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#endif /* _SOC_CHIP_H_ */
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