74f9fe6e58
CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
52 lines
1.1 KiB
Plaintext
52 lines
1.1 KiB
Plaintext
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config CPU_INTEL_HASWELL
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bool
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if CPU_INTEL_HASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select HAVE_MONOTONIC_TIMER
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select SMP
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select MMX
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select SSE2
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select SMM_TSEG
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select SUPPORT_CPU_UCODE_IN_CBFS
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#select AP_IN_SIPI_WAIT
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select TSC_SYNC_MFENCE
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select PARALLEL_MP
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select CPU_INTEL_COMMON
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select NO_FIXED_XIP_ROM_SIZE
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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endif
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