32b99169a5
The semantics of pirq_setup() from previous platforms was to only setup the global pointers for PIC and APIC tables, not to create or modify the tables themselves. Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <acpi/acpi.h>
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#include <amdblocks/amd_pci_util.h>
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#include <FspsUpd.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <soc/pci_devs.h>
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#include <types.h>
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#include <commonlib/helpers.h>
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#include <chip.h>
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#include "gpio.h"
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/* TODO: recheck IRQ tables */
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/*
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*/
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static uint8_t fch_pic_routing[0x80];
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static uint8_t fch_apic_routing[0x80];
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_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
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"PIC and APIC FCH interrupt tables must be the same size");
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static const struct fch_irq_routing {
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uint8_t intr_index;
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uint8_t pic_irq_num;
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uint8_t apic_irq_num;
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} bilby_fch[] = {
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{ PIRQ_A, 8, 16 },
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{ PIRQ_B, 10, 17 },
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{ PIRQ_C, 11, 18 },
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{ PIRQ_D, 12, 19 },
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{ PIRQ_SCI, 9, 9 },
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{ PIRQ_SD, PIRQ_NC, 16 },
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{ PIRQ_SDIO, PIRQ_NC, 16 },
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{ PIRQ_SATA, PIRQ_NC, 19 },
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{ PIRQ_EMMC, PIRQ_NC, 17 },
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{ PIRQ_GPIO, 7, 7 },
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{ PIRQ_I2C2, 6, 6 },
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{ PIRQ_I2C3, 14, 14 },
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{ PIRQ_UART0, 4, 4 },
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{ PIRQ_UART1, 3, 3 },
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{ PIRQ_UART2, 4, 4 },
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{ PIRQ_UART3, 3, 3 },
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/* The MISC registers are not interrupt numbers */
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{ PIRQ_MISC, 0xfa, 0x00 },
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{ PIRQ_MISC0, 0x91, 0x00 },
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{ PIRQ_MISC1, 0x00, 0x00 },
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{ PIRQ_MISC2, 0x00, 0x00 },
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};
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static void init_tables(void)
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{
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const struct fch_irq_routing *entry;
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int i;
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memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
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memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
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for (i = 0; i < ARRAY_SIZE(bilby_fch); i++) {
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entry = bilby_fch + i;
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fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
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fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
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}
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}
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static void pirq_setup(void)
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{
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intr_data_ptr = fch_apic_routing;
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picr_data_ptr = fch_pic_routing;
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}
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static void mainboard_init(void *chip_info)
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{
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struct soc_amd_picasso_config *cfg = config_of_soc();
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if (!CONFIG(BILBY_LPC))
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cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;
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mainboard_program_gpios();
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/* Re-muxing LPCCLK0 can hang the system if LPC is in use. */
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if (CONFIG(BILBY_LPC))
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printk(BIOS_INFO, "eMMC not available due to LPC requirement\n");
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else
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mainboard_program_emmc_gpios();
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}
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static void bilby_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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init_tables();
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = bilby_enable,
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};
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