32d5d5b757
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE` config. TEST=Able to build intel/mtlrvp with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
49 lines
917 B
Plaintext
49 lines
917 B
Plaintext
FLASH 32M {
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SI_ALL 9M {
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SI_DESC 16K
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SI_ME
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}
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SI_BIOS 23M {
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RW_SECTION_A 7604K {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 64
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ME_RW_A(CBFS) 4400K
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}
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RW_MISC 152K {
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 4K {
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SHARED_DATA 4K
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}
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RW_VPD(PRESERVE) 8K
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RW_NVRAM(PRESERVE) 8K
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UNIFIED_MRC_CACHE(PRESERVE) 128K {
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RECOVERY_MRC_CACHE 64K
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RW_MRC_CACHE 64K
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}
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}
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# This section starts at the 16M boundary in SPI flash.
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# MTL does not support a region crossing this boundary,
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# because the SPI flash is memory-mapped into two non-
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# contiguous windows.
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RW_SECTION_B 7604K {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 64
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ME_RW_B(CBFS) 4400K
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO 8M {
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RO_VPD(PRESERVE) 16K
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RO_GSCVD 8K
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RO_SECTION {
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FMAP 2K
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RO_FRID 64
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GBB@4K 12K
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COREBOOT(CBFS)
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}
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}
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}
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}
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