Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
35 lines
828 B
C
35 lines
828 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DIMM_INFO_UTIL_H_
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#define _DIMM_INFO_UTIL_H_
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#include <smbios.h>
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#include <stdint.h>
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/**
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* Convert the SMBIOS bit widths into an SPD encoded width.
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*
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* Use this when setting dimm_info.bus_width if the raw SPD values are not
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* available.
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*/
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uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
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uint16_t data_width);
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/**
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* Convert the SMBIOS size values into the total number of MiB.
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*
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* Use this when setting dimm_info.dimm_size.
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*/
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uint32_t smbios_memory_size_to_mib(uint16_t memory_size,
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uint32_t extended_size);
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/**
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* Convert the SMBIOS form factor to the SPD module type.
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*
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* Use this when setting dimm_info.mod_type.
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*/
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uint8_t
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smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor);
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#endif
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