33c0aac3b6
Before enabling IO decode ranges, current code checks if the DMI SRLOCK is set to prevent inconsistencies between LPC PCI cfg registers and LPC DMI registers, when the latter are locked. DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H, PCH-S and others with discrete PCH packages. So this check is at least incomplete. Further, the lock gets applied by FSP and gets reset on a warm reset. Thus, there is no case where the lock would be already set at the places where the DMI registers get written currently. Drop the checks for the reasons mentioned above. Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 2, 3, 4, 27, 28
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*/
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <intelblocks/dmi.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <soc/bootblock.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100
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#define PCR_PSFX_TO_SHDW_BAR0 0
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#define PCR_PSFX_TO_SHDW_BAR1 0x4
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#define PCR_PSFX_TO_SHDW_BAR2 0x8
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#define PCR_PSFX_TO_SHDW_BAR3 0xC
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#define PCR_PSFX_TO_SHDW_BAR4 0x10
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#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
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#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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static void soc_config_pwrmbase(void)
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{
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/*
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* Assign Resources to PWRMBASE
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* Clear BIT 1-2 Command Register
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*/
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pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* Program PWRM Base */
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pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
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/* Enable Bus Master and MMIO Space */
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pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* Enable PWRM in PMC */
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setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
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}
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void bootblock_pch_early_init(void)
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{
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/*
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* Perform P2SB configuration before any another controller initialization as the
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* controller might want to perform PCR settings.
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*/
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p2sb_enable_bar();
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p2sb_configure_hpet();
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fast_spi_early_init(SPI_BASE_ADDRESS);
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gspi_early_bar_init();
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/*
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* Enabling PWRM Base for accessing
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* Global Reset Cause Register.
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*/
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soc_config_pwrmbase();
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}
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static void soc_config_acpibase(void)
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{
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uint32_t pmc_reg_value;
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uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
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pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
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if (pmc_reg_value != 0xffffffff) {
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/* Disable Io Space before changing the address */
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pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
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~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
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/* Program ABASE in PSF3 PMC space BAR4*/
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pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
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ACPI_BASE_ADDRESS);
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/* Enable IO Space */
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pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
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~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
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}
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}
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void pch_early_iorange_init(void)
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{
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uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
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LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
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/* IO Decode Range */
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if (CONFIG(DRIVERS_UART_8250IO))
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lpc_io_setup_comm_a_b();
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/* IO Decode Enable */
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lpc_enable_fixed_io_ranges(io_enables);
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/* Program generic IO Decode Range */
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pch_enable_lpc();
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}
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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* GPE0_STS, GPE0_EN registers.
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*/
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soc_config_acpibase();
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/* Set up GPE configuration */
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pmc_gpe_init();
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enable_rtc_upper_bank();
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}
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