This patch adds an error msg if intel_microcode_find() is unable to find a microcode for the CPU SKU. TEST=Able to see the error msg in coreboot serial log in case packed with wrong microcode binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4865575a44d2c8c6c3a20c2823a546d8f261e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65285 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
289 lines
6.3 KiB
C
289 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Microcode update for Intel PIII and later CPUs */
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#include <stdint.h>
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#include <stddef.h>
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#include <cbfs.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/microcode.h>
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#include <smp/spinlock.h>
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DECLARE_SPIN_LOCK(microcode_lock)
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struct microcode {
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u32 hdrver; /* Header Version */
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u32 rev; /* Update Revision */
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u32 date; /* Date */
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u32 sig; /* Processor Signature */
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u32 cksum; /* Checksum */
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u32 ldrver; /* Loader Revision */
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u32 pf; /* Processor Flags */
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u32 data_size; /* Data Size */
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u32 total_size; /* Total Size */
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u32 reserved[3];
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};
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struct ext_sig_table {
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u32 ext_sig_cnt;
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u32 ext_tbl_chksm;
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u32 res[3];
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};
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struct ext_sig_entry {
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u32 sig;
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u32 pf;
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u32 chksm;
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};
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static inline u32 read_microcode_rev(void)
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{
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/* Some Intel CPUs can be very finicky about the
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* CPUID sequence used. So this is implemented in
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* assembly so that it works reliably.
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*/
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msr_t msr;
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asm volatile (
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"xorl %%eax, %%eax\n\t"
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"xorl %%edx, %%edx\n\t"
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"movl $0x8b, %%ecx\n\t"
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"wrmsr\n\t"
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"movl $0x01, %%eax\n\t"
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"cpuid\n\t"
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"movl $0x08b, %%ecx\n\t"
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"rdmsr\n\t"
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: /* outputs */
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"=a" (msr.lo), "=d" (msr.hi)
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: /* inputs */
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: /* trashed */
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"ebx", "ecx"
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);
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return msr.hi;
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}
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#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
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static int load_microcode(const struct microcode *ucode_patch)
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{
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u32 current_rev;
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msr_t msr;
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msr.lo = (unsigned long)ucode_patch + sizeof(struct microcode);
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msr.hi = 0;
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wrmsr(IA32_BIOS_UPDT_TRIG, msr);
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current_rev = read_microcode_rev();
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if (current_rev == ucode_patch->rev) {
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printk(BIOS_INFO, "microcode: updated to revision "
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"0x%x date=%04x-%02x-%02x\n", read_microcode_rev(),
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ucode_patch->date & 0xffff, (ucode_patch->date >> 24) & 0xff,
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(ucode_patch->date >> 16) & 0xff);
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return 0;
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}
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return -1;
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}
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void intel_microcode_load_unlocked(const void *microcode_patch)
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{
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u32 current_rev;
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const struct microcode *m = microcode_patch;
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if (!m) {
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printk(BIOS_ERR, "microcode: failed because no ucode was found\n");
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return;
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}
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current_rev = read_microcode_rev();
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/* No use loading the same revision. */
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if (current_rev == m->rev) {
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printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n");
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return;
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}
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#if ENV_RAMSTAGE
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/*SoC specific check to update microcode*/
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if (soc_skip_ucode_update(current_rev, m->rev)) {
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printk(BIOS_DEBUG, "Skip microcode update\n");
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return;
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}
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#endif
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printk(BIOS_INFO, "microcode: load microcode patch\n");
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if (load_microcode(m) < 0)
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printk(BIOS_ERR, "microcode: Update failed\n");
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}
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uint32_t get_current_microcode_rev(void)
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{
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return read_microcode_rev();
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}
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uint32_t get_microcode_rev(const void *microcode)
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{
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return ((struct microcode *)microcode)->rev;
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}
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uint32_t get_microcode_size(const void *microcode)
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{
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return ((struct microcode *)microcode)->total_size;
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}
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uint32_t get_microcode_checksum(const void *microcode)
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{
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return ((struct microcode *)microcode)->cksum;
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}
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static struct ext_sig_table *ucode_get_ext_sig_table(const struct microcode *ucode)
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{
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struct ext_sig_table *ext_tbl;
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/* header + ucode data blob size */
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u32 size = ucode->data_size + sizeof(struct microcode);
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ssize_t ext_tbl_len = ucode->total_size - size;
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if (ext_tbl_len < (ssize_t)sizeof(struct ext_sig_table))
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return NULL;
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ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size);
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if (ext_tbl_len < (sizeof(struct ext_sig_table) +
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ext_tbl->ext_sig_cnt * sizeof(struct ext_sig_entry)))
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return NULL;
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return ext_tbl;
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}
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static const void *find_cbfs_microcode(void)
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{
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const struct microcode *ucode_updates;
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struct ext_sig_table *ext_tbl;
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size_t microcode_len;
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u32 eax;
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u32 pf, rev, sig, update_size;
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msr_t msr;
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struct cpuinfo_x86 c;
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ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, µcode_len);
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if (ucode_updates == NULL)
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return NULL;
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rev = read_microcode_rev();
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eax = cpuid_eax(1);
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get_fms(&c, eax);
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sig = eax;
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pf = 0;
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if ((c.x86_model >= 5) || (c.x86 > 6)) {
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msr = rdmsr(IA32_PLATFORM_ID);
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pf = 1 << ((msr.hi >> 18) & 7);
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}
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printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n",
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sig, pf, rev);
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while (microcode_len >= sizeof(*ucode_updates)) {
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/* Newer microcode updates include a size field, whereas older
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* containers set it at 0 and are exactly 2048 bytes long */
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if (ucode_updates->total_size) {
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update_size = ucode_updates->total_size;
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} else {
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printk(BIOS_SPEW, "Microcode size field is 0\n");
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update_size = 2048;
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}
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/* Checkpoint 1: The microcode update falls within CBFS */
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if (update_size > microcode_len) {
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printk(BIOS_WARNING, "Microcode header corrupted!\n");
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break;
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}
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if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf))
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return ucode_updates;
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/* Check if there is extended signature table */
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ext_tbl = ucode_get_ext_sig_table(ucode_updates);
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if (ext_tbl != NULL) {
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int i;
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struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
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for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) {
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if ((sig == entry->sig) && (pf & entry->pf)) {
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return ucode_updates;
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}
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}
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}
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ucode_updates = (void *)((char *)ucode_updates + update_size);
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microcode_len -= update_size;
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}
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return NULL;
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}
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const void *intel_microcode_find(void)
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{
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static bool microcode_checked;
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static const void *ucode_update;
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if (microcode_checked)
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return ucode_update;
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/*
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* Since this function caches the found microcode (NULL or a valid
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* microcode pointer), it is expected to be run from BSP before starting
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* any other APs. This sequence is not multithread safe otherwise.
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*/
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ucode_update = find_cbfs_microcode();
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microcode_checked = true;
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return ucode_update;
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}
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void intel_update_microcode_from_cbfs(void)
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{
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const void *patch = intel_microcode_find();
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spin_lock(µcode_lock);
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intel_microcode_load_unlocked(patch);
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spin_unlock(µcode_lock);
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}
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void intel_reload_microcode(void)
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{
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if (!CONFIG(RELOAD_MICROCODE_PATCH))
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return;
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const struct microcode *m = intel_microcode_find();
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if (!m) {
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printk(BIOS_ERR, "microcode: failed because no ucode was found\n");
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return;
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}
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printk(BIOS_INFO, "microcode: Re-load microcode patch\n");
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if (load_microcode(m) < 0)
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printk(BIOS_ERR, "microcode: Re-load failed\n");
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}
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#if ENV_RAMSTAGE
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__weak int soc_skip_ucode_update(u32 current_patch_id,
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u32 new_patch_id)
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{
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return 0;
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}
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#endif
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