348a6d519c
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de. Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc. Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
181 lines
4.9 KiB
C
181 lines
4.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree.
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*/
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <stdint.h>
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#include <fsp/util.h>
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#include <soc/pci_devs.h>
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#define SVID_CONFIG1 1
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#define SVID_CONFIG3 3
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#define SVID_PMIC_CONFIG 8
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#define MEM_DDR3 0
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#define MEM_LPDDR3 1
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enum lpe_clk_src {
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LPE_CLK_SRC_XTAL,
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LPE_CLK_SRC_PLL,
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};
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enum usb_comp_bg_value {
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USB_COMP_BG_575_MV = 7,
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USB_COMP_BG_650_MV = 6,
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USB_COMP_BG_550_MV = 5,
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USB_COMP_BG_537_MV = 4,
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USB_COMP_BG_625_MV = 3,
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USB_COMP_BG_700_MV = 2,
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USB_COMP_BG_600_MV = 1,
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USB_COMP_BG_675_MV = 0,
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};
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struct soc_intel_braswell_config {
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uint8_t enable_xdp_tap;
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uint8_t clkreq_enable;
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/* Disable SLP_X stretching after SUS power well loss. */
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int disable_slp_x_stretch_sus_fail;
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/* LPE Audio Clock configuration. */
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enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int emmc_acpi_mode;
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int sd_acpi_mode;
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int lpe_acpi_mode;
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/* Allow PCIe devices to wake system from suspend. */
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int pcie_wake_enable;
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/* Program USB2_COMPBG register.
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* [10:7] - select vref to AFE port
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* x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
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* x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
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*/
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enum usb_comp_bg_value usb_comp_bg;
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during
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* MemoryInit.
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*/
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UINT16 PcdMrcInitTsegSize;
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UINT16 PcdMrcInitMmioSize;
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UINT8 PcdMrcInitSpdAddr1;
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UINT8 PcdMrcInitSpdAddr2;
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UINT8 PcdIgdDvmt50PreAlloc;
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UINT8 PcdApertureSize;
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UINT8 PcdGttSize;
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UINT8 PcdLegacySegDecode;
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UINT8 PcdDvfsEnable;
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UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */
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/*
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* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
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* These are configuration values that are passed to FSP during
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* SiliconInit.
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*/
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UINT8 PcdSdcardMode;
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UINT8 PcdEnableHsuart0;
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UINT8 PcdEnableHsuart1;
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UINT8 PcdEnableAzalia;
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UINT8 PcdEnableSata;
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UINT8 PcdEnableXhci;
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UINT8 PcdEnableLpe;
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UINT8 PcdEnableDma0;
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UINT8 PcdEnableDma1;
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UINT8 PcdEnableI2C0;
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UINT8 PcdEnableI2C1;
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UINT8 PcdEnableI2C2;
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UINT8 PcdEnableI2C3;
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UINT8 PcdEnableI2C4;
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UINT8 PcdEnableI2C5;
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UINT8 PcdEnableI2C6;
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UINT8 PunitPwrConfigDisable;
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UINT8 ChvSvidConfig;
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UINT8 DptfDisable;
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UINT8 PcdEmmcMode;
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UINT8 PcdUsb3ClkSsc;
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UINT8 PcdDispClkSsc;
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UINT8 PcdSataClkSsc;
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UINT8 Usb2Port0PerPortPeTxiSet;
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UINT8 Usb2Port0PerPortTxiSet;
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UINT8 Usb2Port0IUsbTxEmphasisEn;
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UINT8 Usb2Port0PerPortTxPeHalf;
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UINT8 Usb2Port1PerPortPeTxiSet;
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UINT8 Usb2Port1PerPortTxiSet;
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UINT8 Usb2Port1IUsbTxEmphasisEn;
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UINT8 Usb2Port1PerPortTxPeHalf;
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UINT8 Usb2Port2PerPortPeTxiSet;
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UINT8 Usb2Port2PerPortTxiSet;
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UINT8 Usb2Port2IUsbTxEmphasisEn;
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UINT8 Usb2Port2PerPortTxPeHalf;
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UINT8 Usb2Port3PerPortPeTxiSet;
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UINT8 Usb2Port3PerPortTxiSet;
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UINT8 Usb2Port3IUsbTxEmphasisEn;
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UINT8 Usb2Port3PerPortTxPeHalf;
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UINT8 Usb2Port4PerPortPeTxiSet;
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UINT8 Usb2Port4PerPortTxiSet;
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UINT8 Usb2Port4IUsbTxEmphasisEn;
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UINT8 Usb2Port4PerPortTxPeHalf;
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UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
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UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
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UINT8 PcdSataInterfaceSpeed;
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UINT8 PcdPchUsbSsicPort;
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UINT8 PcdPchUsbHsicPort;
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UINT8 PcdPcieRootPortSpeed;
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UINT8 PcdPchSsicEnable;
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UINT32 PcdLogoPtr;
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UINT32 PcdLogoSize;
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UINT8 PcdRtcLock;
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UINT8 PMIC_I2CBus;
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UINT8 ISPEnable;
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UINT8 ISPPciDevConfig;
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UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/
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UINT8 I2C0Frequency; /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */
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UINT8 I2C1Frequency;
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UINT8 I2C2Frequency;
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UINT8 I2C3Frequency;
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UINT8 I2C4Frequency;
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UINT8 I2C5Frequency;
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UINT8 I2C6Frequency;
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UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/
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UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/
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UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/
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UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/
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UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/
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};
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extern struct chip_operations soc_intel_braswell_ops;
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#endif /* _SOC_CHIP_H_ */
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