355dc1e66a
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__
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#define __SOC_NVIDIA_TEGRA_APBMISC_H__
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#include <stdint.h>
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struct apbmisc {
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u32 reserved0[2]; /* ABP_MISC_PP_ offsets 00 and 04 */
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u32 pp_strapping_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
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u32 reserved1[6]; /* ABP_MISC_PP_ offsets 0C-20 */
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u32 pp_config_ctl; /* _CONFIG_CTL_0, offset 24 */
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u32 reserved2[6]; /* APB_MISC_PP_ offsets 28-3C */
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u32 pp_pinmux_global; /* _PINMUX_GLOBAL_0, offset 40 */
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};
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#define PP_CONFIG_CTL_TBE (1 << 7)
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#define PP_CONFIG_CTL_JTAG (1 << 6)
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#define PP_PINMUX_CLAMP_INPUTS (1 << 0)
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enum {
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MISC_GP_HIDREV = 0x804
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};
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struct tegra_revision {
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int hid_fam;
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int chip_id;
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int major;
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int minor;
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};
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void enable_jtag(void);
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void clamp_tristate_inputs(void);
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void tegra_revision_info(struct tegra_revision *id);
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enum {
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PP_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4,
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PP_STRAPPING_OPT_A_RAM_CODE_MASK =
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0xF << PP_STRAPPING_OPT_A_RAM_CODE_SHIFT,
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};
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#endif /* __SOC_NVIDIA_TEGRA_APBMISC_H__ */
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